TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 49

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.
2.1
Address
0000 H
0C
0D
1C
1D
0A
0B
0E
1A
1B
1E
01
02
03
04
05
06
07
08
09
0F
10
11
12
13
14
15
16
17
18
19
1F
On-Chip Peripherals Functions
Special Function Register (SFR)
transfers are performed through the special function register (SFR). The SFR is mapped on
address 0000
TMP86FM48.
The TMP86FM48 adopts the memory mapped I/O system, and all peripheral control and data
Figure 2.1.2 indicate the special function register (SFR) and data buffer register (DBR) for
TC3DRB (Timer register 3B)
Note 1: Do not access reserved areas by the program.
Note 2: −: Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation
SIO1SR (SIO1 status)
SIO2SR (SIO2 status)
Figure 2.1.1 The Special Function Register (SFR) for TMP86FM48 (1/2)
Read
instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
P6CR1 (P6 Port input/output control)
P0OUTCR (P0 Port output control)
P1OUTCR (P1 Port output control)
P5OUTCR (P5 Port output control)
TC3CR (Timer Counter 3 control)
TC2CR (Timer Counter 2 control)
TC5CR (Timer Counter 5 control)
TC1CR (Timer counter 1 control)
ADCCR1 (AD control register 1)
ADCCR2 (AD control register 2)
TC3DRA (Timer register 3A)
SIO1BUF (SIO1 data buffer)
SIO2BUF (SIO2 data buffer)
P0DR (P0 Port output latch)
P1DR (P1 Port output latch)
P2DR (P2 Port output latch)
P3DR (P3 Port output latch)
P5DR (P5 Port output latch)
P6DR (P6 Port output latch)
P7DR (P7 Port output latch)
P8DR (P8 Port output latch)
H
TC5DR (Timer register 5)
SIO1CR (SIO1 control)
SIO2CR (SIO2 control)
to 003F
Reserved
Reserved
Reserved
Reserved
Reserved
H
, DBR is mapped on address 1F80
Write
−
−
−
Figure 2.1.1 to
86FM48-45
Address
0020 H
2A
2B
2C
2D
2E
3A
3B
3C
3D
3E
21
22
23
24
25
26
27
28
29
2F
30
31
32
33
34
35
36
37
38
39
3F
ADCDR2 (AD result register 2)
ADCDR1 (AD result register 1)
H
Read
to 1FFF
−
−
EINTCR (External interrupt control)
P3OUTCR (P3 Port output control)
EIR E (Interrupt enable register)
EIR H (Interrupt enable register)
EIR L (Interrupt enable register)
TBTCR (TBT/TG/DVO control)
TC1DRAH (Timer register 1A)
TC1DRBH (Timer register 1B)
P6CR2 (P6 Port input control)
TC1DRAL (Timer register 1A)
TC1DRBL (Timer register 1B)
SYSCR1 (System control 1)
SYSCR2 (System control 2)
PSW (Program status word)
TC2DRH (Timer register 2)
TC2DRL (Timer register 2)
IL H (Interrupt latch)
IL E (Interrupt latch)
IL L (Interrupt latch)
H
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
.
WDTCR1 (Watchdog timer control)
WDTCR2 (Watchdog timer control)
Write
TMP86FM48
−
−
2007-08-24