tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 113

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
8 TMUX Registers
Table 116. TMUX_THS_ERR_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W)
Table 117. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W )
Agere Systems Inc.
Address
Address
0x4004A
0x40049 15:10
12:10
8:6
4:0
Bit
Bit
15
14
13
9
5
9
TMUX_TH1H2INVORNDF Transmit H1 H2 Corrupt or NDF. When 0, causes an
TMUX_TH1H2INVEN[3:1] Transmit H1 H2 Corrupt Enable. When 1, cause the
TMUX_TA2ERRINS[4:0]
TMUX_RTOAC_D412MODE Receive TOAC DCC4 to DCC12 Only Mode. When
TMUX_TTOAC_D412MODE Transmit TOAC DCC4 to DCC12 Only Mode.
TMUX_RTOAC_D13MODE
TMUX_TAPSBABINS
TMUX_RTOAC_OEPINS
(continued)
Name
—
Name
—
Reserved.
Transmit APS Babble Insert. When 1, causes an
inconsistent APS byte (K1[7:0], K2[7:3]) to be inserted
into the outgoing STS-3/STM-1 (AU-4) frame.
output H1 and H2 bytes of the STS-3/STM-1 (AU-4) sig-
nal to be corrupted on a per STS-1 basis. In the AU-4
mode, only control bit 1 is used.
invalid pointer to be inserted into the output H1 and H2
bytes; otherwise, a continuous NDF condition (1001) is
sent.
Transmit Frame Error Insert Value. These bits specify
the number of consecutive frames to be inserted with a
frame error is inserted in the outgoing A2 byte. This
number of errored frames is sent each time a rising edge
is observed on the SMPR_BER_INSRT
signal.
1, causes the RTOAC data signal to carry only a par-
ity byte followed by DCC4 to DCC12 bytes. The clock
rate is 640 kHz. If this control bit is a logic 0 and
TMUX_RTOAC_D13MODE is a logic zero, then the
receive TOAC channel is in full access mode.
Receive TOAC DCC1 to DCC3 Only Mode. When
1, causes the RTOAC data signal to carry only a par-
ity byte followed by DCC1 to DCC3 bytes. The clock
rate is 260 kHz. If this control bit is a logic 0 and
TMUX_RTOAC_D412MODE is a logic zero, then the
receive TOAC channel is in full access mode.
Receive TOAC Odd or Even Parity Insert. When 1,
forces receive the output TOAC parity bit to be even;
otherwise, the parity is odd.
Reserved.
When 1, causes DCC4 to DCC12 in the outgoing
frame to be inserted from the TTOAC channel. The
TTOAC clock rate is 640 kHz. If this control bit is a
logic 0 and TMUX_TTOAC_D13MODE is a logic
zero, then the transmit TOAC channel is in full
access mode.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Function
Function
TMXF28155/51 Super Mapper
(Table
65) input
Default
Default
Reset
Reset
0x00
000
0x0
000
0
0
0
0
0
0
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