tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 59

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
5 Timing Characteristics
ADDR [19:0] Address is asynchronously passed from the host bus to the internal bus. The address will be avail-
DATA [15:0]
RWN (Input) The read (H) write (L) signal is always high during a read cycle.
CSN (Input) Chip select is an active-low signal.
DTN (Output) Data transfer acknowledge (active-low). DTN is driven asynchronously based on the arrival of CSN,
ADSN (Input) Address strobe is active-low.
DSN (Input) Data strobe is active-low.
Agere Systems Inc.
Figure 17. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0)
ADDR[19:0]
DATA[15:0]
able throughout the entire cycle.
Read data on the internal bus is only valid for one clock cycle; therefore, a latch is necessary to meet
the correct timing on the host bus.
DSN, and ADSN. DTN is driven high while the internal bus transaction is in progress. There is no
need to provide synchronization to outgoing signals in this mode. DTN is driven high and then placed
in a high-impedance state when either ADSN or DSN is deasserted. DTN will become 3-stated when
CSN is high.
ADSN
RWN
CSN
DSN
DTN
HIGH Z
tAVADSF
tAVDSF
tCSFDSF
tCSFDTR
(continued)
HIGH Z
tDSFDTF
tDTVDV
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
tADSRDTR
tDSNRAI
tADSRAI
TMXF28155/51 Super Mapper
tADSRD3
tAICSR
tCSRDT3
HIGH Z
HIGH Z
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