tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 517

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
TMXF28155/51 Super Mapper
May 2001
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
(continued)
21.23 HDLC Functional Description
The Super Mapper framer is capable of inserting and extracting HDLC data to and from multiple logical channels.
The system may specify any bit as an HDLC channel. For ESF, DDS, and CEPT framing formats, the facility data
link (FDL) bit may be programmed as a logical HDLC channel. Multiple bits within a time slot may be concatenated
to form a logical HDLC channel. The maximum number of bits in a logical channel is 8 bits (all within a single time
slot) and corresponds to a maximum data rate of 64 kbits/s. Multiple logical HDLC channels may be assigned to a
single payload time slot.
Received data from a HDLC channel is placed into a 128-byte FIFO. Transmit HDLC channels are read from a sep-
arate 128-byte FIFO.
Once the HDLC channels are defined and the HDLC is enabled, the framer extracts and inserts the HDLC frames
in these channels. The function of the receive and transmit HDLC sections will be described separately.
21.24 HDLC Operation
This section describes the standard HDLC functions performed by the framer’s HDLC block. The HDLC transmitter
accepts parallel data from the transmit FIFO, converts it to a serial bit stream, provides bit stuffing as necessary,
adds the CRC and the opening and closing flags, and sends the framed serial bit stream to the transmit framer.
The HDLC receiver unit receives time slot data from the receive framer, identifies frames for proper format, recon-
structs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO. HDLC frames
on the serial link have the following format.
Table 595. HDLC Frame Format
Opening Flag
User Data Field
Frame Check Sequence (CRC)
Closing Flag
01111110
8 bits (multiple of 8 bits)
16 bits
01111110
All bits between the opening flag and the CRC are considered user payload. User payload data such as the
address, control, and information fields are fetched from the transmit FIFO for transmission. Received user payload
data is stored in the receive FIFO buffers. The 16 bits preceding the closing flag are the frame check sequence or
cyclic redundancy check (CRC) bits.
21.24.1 Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing)
The HDLC protocol recognizes three special bit patterns: flags, aborts, and idles. These patterns have the common
characteristic of containing at least six consecutive ones. A user data byte can contain one of these special pat-
terns. Transmitter zero-bit stuffing is done on user data and CRC fields of the frame to avoid transmitting one of
these special patterns. Whenever five ones occur between flags, a 0 bit is automatically inserted after the fifth 1,
prior to transmission of the next bit. On the receive side, if five successive ones are detected followed by a 0, the 0
is assumed to have been inserted and is deleted (bit destuffing).
21.24.2 Flags
All flags* have the bit pattern 01111110 and are used for frame synchronization. The framer’s HDLC block auto-
matically sends one flag at the beginning of each frame. If the FRM_HTIDLE
(Table
435) bit is cleared to 0, the
FLAG byte (01111110) is continuously sent between frames if no data is present in the FIFO. If the FRM_HTIDLE
bit is set to 1, the HDLC block sends continuous FRM_IDLE
(Table
349) bytes (11111111) when the transmit FIFO
is empty. Once there is data in the transmit FIFO, an opening flag is sent, followed by the frame. During transmis-
sion, two successive flags will not share the intermediate 0.
* Regardless of the time-fill byte used, there always is an opening and closing flag with each frame. Back-to-back frames are separated by two
flags.
Agere Systems Inc.
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