tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 568

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
22 Cross Connect (XC) Block Functional Description
22.9 Transmit and Receive Path Overhead Access Channel I/O Configuration
The cross connect allows selection of transmit and receive POAC channels from either the TMUX block or SPE
mapper to the external I/O pins as shown in
An output enable and a select register bit is provided for transmit and receive POAC. The transmit POAC clock and
sync output signals are enabled with bit XC_TPOAC_EN
is selected with register bit XC_TSTS1_TUG3
are enabled with bit XC_RPOAC_EN
XC_RSTS1_TUG3
568
(Table
EXTERNAL I/O
LINERXSYNC[29]
LINETXSYNC[29]
LINERXDATA[29]
LINETXDATA[29]
LINERXCLK[29]
LINETXCLK[29]
TPG
RXDATAEN
TXDATAEN
TPG_DATA
462).
RLSC52
TLSC52
XC3_TSOURCE_ID[1:0]
Figure 96. NSMI Interface Cross Connect
(Table
Figure
462) and the source, SPE mapper or TMUX block, is selected with bit
(Table
XC
XC_PDATA[1—29][7:0]
97.
462). The receive POAC clock, data, and sync output signals
(Table
462) and the source, SPE Mapper or TMUX block,
XC_SYNC[1—29][7:0]
(continued)
M13_NSMI_CLK
M13_NSMI_EN
M13_NSMI_SYNC
XC3_NSMI_DATA
M13_DNSMI_CLK
M13_DNSMI_EN
M13_DNSMI_SYNC
M13_DNSMI_DATA
XCP_NSMI_DATA
SPE_NSMI_SYNC
SPE_NSMI_CLKEN
SPE_DNSMI_SYNC
SPE_DNSMI_CLKEN
SPE_DNSMI_DATA
TSMI_D
TSMI_CTL
TSMI_CLK
RSMI_D
RSMI_CLKO
RSMI_CTLO
RSMI_CTLI
RSMI_CLKI
FRM
M13
SPE
Agere Systems Inc.
May 2001
5-9195(F)r.1