tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 357

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

May 2001
16 Microprocessor Interface Functional Description
The PM counter control signal controls the transfer and reset of all performance monitoring registers (collecting
events/statistics). The source of this signal is configurable and can come from external pin (PMRST pin T25), an
internal timer, or be controlled by software, depending on the SMPR_PMMODE[1:0] bits
described as follows:
SMPR_PMMODE[1:0] = 00, 10: PM counter control is sourced from external pin PMRST.
SMPR_PMMODE[1:0] = 01: PM counter control is sourced from internal 1 second timer. Writing a logic one to the
SMPR_PMRESET bit
control signal within 10 MPCLK clock cycles. The timer is based on the period of the MPCLK and the programmed
value of the registers in
is determined by the combined delay of the programmed registers. The device pin, PMRST, is enabled as an out-
put.
SMPR_PMMODE[1:0] = 11: The PM counter control signal is software controlled. Writing a logic one to the
SMPR_PMRESET bit will cause a PM reset within 10 MPCLK cycle times after writing. This pulse will be
100 cycles high and 100 cycles low at the MPCLK frequency. During this 200 cycle time, writing to PM bit will have
no effect. The device pin, PMRST, is enabled as an output.
Agere Systems Inc.
PM COUNTER CONTROL
PM COUNT EVENT
PM COUNT EVENT CLOCK
MPUCLK
(Table
(REGISTER SMPR_GCR bits[9:8])
(REGISTER SMPR_GTR bit 8)
Table 72
RESET
SMPR_PMRESET
SMPR_PMRESET_HIGH_COUNT
SMPR_PMRESET_LOW_COUNT
SMPR_PMMODE
65, bit 8) will reset the timer so that a transition occurs on the internal PM counter
PMRSTI
and
Figure 20. PM Reset Signal Generation
COUNTER
RUNNING
Table
1/2 SECOND
COUNTERS
DELAY
Figure 19. PM Reset Counter
73. Once initially reset and synchronized, the PM counter reset interval
MPU BLOCK
ENABLE
EXTERNAL
(SMPR_PMMODE[1:0] = 00, 10)
SOFTWARE CONTROLLED
(SMPR_PMMODE[1:0] = 11)
FREE RUNNING
(SMPR_PMMODE[1:0] = 01)
MPUCLK
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
PM COUNTER
MPU READABLE
COUNTER
HOLDING
(continued)
PMRST (TO BLOCKS)
SMPR_PMMODE[1:0] = 01, 11
SMPR_PMMODE[1:0] = 00, 10
PMRSTO
OUTPUT DISABLED
OUTPUT ENABLED
BUFFERED
MPUCLK
MPU READ HOLDING
(ONE PER BLOCK)
(Table
REGISTER
67, bits 9:8),
5-9040(F)r.3
5-9931(F)
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