tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 285

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers
Table 389. FRM_PMLR8, Performance Monitor Link Register 8 (COR)
* See
Table 390. FRM_PMLR9, Performance Monitor Link Register 9 (COR)
* See
Table 391. FRM_PMLR10, Performance Monitor Link Register 10 (COR)
* See
Table 392. FRM_PMLR11, Performance Monitor Link Register 11 (COR)
* See
Table 393. FRM_PMLR12, Performance Monitor Link Register 12 (COR)
* See
Agere Systems Inc.
Address*
Address*
Address*
Address*
Address*
0x8LP8B
0x8LP87
0x8LP88
0x8LP89
0x8LP8A
Table 381
Table 381
Table 381
Table 381
Table 381
15:0 FRM_CENT[15:0] Sa6 = 001x Event Counter. This register contains the
for values of L and P.
for values of L and P.
for values of L and P.
for values of L and P.
for values of L and P .
15:0 FRM_FBEC[15:0] Frame Bit Error Counter.
15:0 FRM_CEC[15:0] CRC Error Counter. This register contains the 16-bit count
15:0 FRM_REC[15:0] Receive E-bit Counter. This register contains the 16-bit
15:0 FRM_CETE[15:0] Sa6 = 00x1 Event Counter. This register contains the
Bit
Bit
Bit
Bit
Bit
Name
Name
Name
Name
Name
of received CRC errors. CRC errors are not counted during
loss of CRC multiframe alignment.
count of received E bit = 0 events. E bit = 0 events are not
counted during loss of CEPT CRC-4 multiframe alignment.
16-bit count of received Sa6 = 001x events. The Sa6 code
is detected synchronously to the CRC-4 multiframe and is
not counted during loss of CRC-4 multiframe alignment.
This detection is not qualified by Sa5 = 1.
DS1: This register contains the 16-bit count of received
framing bit errors. Framing bit errors are not counted dur-
ing loss of frame alignment. (T1.231 section 6.1.1.2.2.)
CEPT: This register contains the 16-bit count of received
frame alignment signal errors. Optionally, bit 2 of non-FAS
frames can be counted.
Note: A FAS with errors in two or more bit positions is
16-bit count of received Sa6 = 00x1 events. The Sa6
code is detected synchronously to the CRC-4 multiframe
and is not counted during loss of CRC-4 multiframe align-
ment. This detection is not qualified by Sa5 = 1.
(continued)
only counted once.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Function
Function
Function
Function
Function
TMXF28155/51 Super Mapper
Reset Default
Reset Default
Reset Default
Reset Default
Reset Default
0x0000
0x0000
0x0
0x0
0x0
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