tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 513

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description
21.22.8 Transmit Facility Data Link Functional Description
This block performs the transmission of D bits into SLC -96 superframes, SA bits into CEPT multiframes, and data
link bits into DDS frames.
For SLC -96 frames, the D bits are always sourced from this block when the block is enabled for insertion
(FRM_DS1I
in the stack with the D bits.
For CEPT frames, the Sa bits are sourced from either the Sa stack or outside of the data link block. The data link
block only responds with valid data when selected by the Sa source control bits (FRM_SA4SC—FRM_SA8SC
(Table
For DDS frames, the data link bits are always sourced from this block when this block is enabled for insertion
(FRM_DS1I).
This block also provides the capability to transmit BOMs in the data link channel of ESF links.
All frame types:
21.22.9 SLC -96 Superframe Transmit Data Link
When enabled for insertion, this block will always source the D bits to any SLC -96 Tx link. The delineator bits ( SLC -
96 Fs frame), which bound the 24 D bits, are also sourced from this block.
The 12-frame SLC -96 superframe is composed of a terminal frame (F
a combined signaling (F
SLC -96 data link. The FDL stack bits are inserted into the signaling and data link subframe position in the super-
frame. Seventy-two superframes are required to deliver the 24 D bits and 12-bit delineator. The front-end delineator
is 00111, which is followed by 24 D bits and trailed by 0001110. The alignment of the F
is determined and indicated by the frame aligner block.
The SLC -96 F
Table 592. Shared Tx FDL Stack Format for SLC -96 Frames
* The value held in the bits left blank should be ignored by the host.
The transmission of the SLC -96 stack will take 9 ms to complete, during which time the host should refill the system
stack if the D bits need to change.
Near the beginning of each SLC -96 superframe, the Tx data link block will determine whether a new set of D bits is
available to be transmitted.
Agere Systems Inc.
Support clear-on-read status and interrupt bits based on the setting of the input select signal.
Provides storage for D bits and delineator bits for transmission on SLC -96 links.
Provides interrupt for stack empty.
Provides host access to stack using processor clock.
Performs retransmission of stack when update is yet to be performed.
Word
1*
2*
3*
4*
0
412)).
(Table
S
SB2 SB3
C1
15
bits are stored in the shared Tx stack as shown in
0
0
0
412)). The D-bit delineator bits ( SLC -96 Fs frame) are also sourced from this block and stored
C2
14
0
0
0
S
) frame and data link. The subframe shares establishing the signaling frame (F
M1
C3
13
0
0
0
M2
C4
12
1
0
0
M3
C5
11
1
0
0
C6
A1
10
1
0
0
C7
A2
9
0
0
0
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
C8
S1
8
0
0
0
C9
S2
Table
7
0
0
0
T
) alternating with a subframe that consists of
C10 C11 SB1
S3
592.
6
1
0
0
(continued)
TMXF28155/51 Super Mapper
S4
5
1
0
0
SB4
4
1
0
0
S
bits within the superframe
3
0
0
0
0
0
2
0
0
0
0
0
S
1
0
0
0
0
0
) and
513
0
0
0
0
0
0