tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 460

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
20 M13/M23 MUX/DeMUX Block Functional Description
20.4 M13 Functional Description
In the descriptions below, some of the register bits exist for each of the DS1, E1, or DS2 signals. The names of
these register bits have a lower case x or a y suffix to show that there are actually 28 or 7 of them, respectively.
20.5 M13 Multiplexing Path
There are seven M12 multiplexers and one M23 multiplexer on the transmit side of this M13 block and all of them
can operate independently. Twenty-eight DS1 inputs in groups of four, or twenty-one E1 input signals in groups of
three can feed into individual M12 MUXs, while the M23 MUX can take DS2 signals from outputs of M12 MUXs, or
direct DS2 inputs, or loopback deMUXed DS2s.
20.5.1 M12 Multiplexers
M12 multiplexers have four operation modes provisionable through M13_M12_MODEy[1:0]
20.5.2 DS1/E1 Interface
The incoming DS1/E1 clock signals (XC_DS1CLK[28—1]) are first checked for activity or loss of clock (LOC). This
is reported to the microprocessor via bits M13_DS1_LOC[28:1]
inserted into the associated DS1/E1 channel using the clock from external pins, DS1XCLK/E1XCLK (AD16/AC17)
(Table
The incoming DS1/E1 data signals are retimed immediately by the associated clocks. The edge of the clocks that is
used to retime the data is user provisionable to either the rising edge (M13_RDS1_EDGEx = 1
ing edge (M13_RDS1_EDGEx = 0).
After being retimed, the incoming data stream is checked for AIS. When the input is DS1, the M13 will declare AIS
if the input data is logic 0 for fewer than 9 out of 8192 clock periods (T1.231). When the input is E1, AIS is declared
if there are less than 3 zeros in each of two consecutive 512-bit periods and cleared when each of two consecutive
512-bit periods contains more than 2 zeros (G.775). If AIS is detected on any of the DS1/E1 inputs
(XC_DS1DATA[28—1]), the associated M13_DS1_AIS_DET[28:1]
460
M13_M12_MODEy[1:0] = 00: the M12 operates as the first stage of M13 multiplexing. It takes 4 DS1s
(M13_DS1_E1Ny =
into the M23 MUX. In this mode, the DS1/E1 clocks are independent inputs to the block. There should be no valid
DS2 input (XC_DS2M23DATAy). This is the default mode.
M13_M12_MODEy[1:0] = 01: the M12 operates as an independent multiplexer. It takes 4 DS1s
(M13_DS1_E1Ny = 1) or 3 E1s (M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be sent directly to
the DS2 output (M13_DS2M12DATAy) of the block and not be passed to M23 MUX input. In this mode, the
DS1/E1 clocks are independent inputs to the block and a DS2 input clock (XC_DS2M12CLKy) is required.
M13_M12_MODEy[1:0] = 10: the M12 operates as an independent multiplexer. It takes 4 DS1s (register bit
M13_DS1_E1Ny = 1) or 3 E1s (register bit M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be sent
directly to the DS2 output (M13_DS2M12DATAy) of the block and not be passed to M23 MUX input. In this mode,
the associated DS1/E1 clocks are outputs from the block and derived from the DS2 input clock
(XC_DS2M12CLKy).
M13_M12_MODEy[1:0] = 11: the M12 is idle. The output from this M12 multiplexer will be held low.
3).
1(Table
263)) or 3 E1s (M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be fed
(Table
(Table
247). Once LOC is detected, AIS will be
248) bit is set.
(continued)
(Table
(Table
Agere Systems Inc.
263):
264)) or fall-
May 2001