tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 522

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
21.25 Framer Phase-Lock Loop (PLL)
The Super Mapper incorporates an internal PLL to generate transmit path line clocks for the framers at DS1, and
E1 from an external system clock (device pin CLKIN_PLL (AD24)).
The external system clock is multiplied by an analog phase-locked loop (PLL) and fractionally divided down to
obtain the required line clock frequencies.
The PLL may be programmed for eight different external system clocks with the device pins: MODE2_PLL (AB21)
(MSB), MODE1_PLL (AE24), and MODE0_PLL (AF24) (LSB), as shown in
Table 597. Clock Mode Programming for PLL Mode Device Pins
The PLL is used when framer bit PLL_BYPAS = 0
external clock at the system interface is used as the line clock. An example would be when the framers are pro-
grammed for a CHI interface at 2.048 MHz and the frames are programmed for E1, the PLL may be bypassed and
the CHI system clock may be used as the line clock.
The PLL may be powered down when not in use with microprocessor register bit SMPR_MPU_CG_PWRDN
(Table
522
Clock Select MODE2_PLL, MODE1_PLL, MODE0_PLL
70) set to 1.
M O D E 2_ P L L
M O D E 1_ P L L
M O D E 0_ P L L
C L K IN _ P L L
000
001
010
011
100
101
110
111
Figure 66. Framer PLL
FR AC TIO N A L D IV ID E R
A N A L O G P LL
(Table
A N D
M P U R EG IST ER B IT
M P U _ C G _ P W R D N
301). When PLL_BYPAS = 1, the PLL is bypassed and an
System Clock Frequency (MHz) CLKIN_PLL
FR A M E R BL O C K
C L O C K S TO
(continued)
Table 597
Reserved (do not use)
26.624
16.384
51.84
19.44
8.192
4.096
2.048
below.
Agere Systems Inc.
May 2001
5-9075(F)