tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 264

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers
Table 364. FRM_SGR6, Receive Signaling Global Register 6
Table 365. FRM_SGR7, Receive Signaling Global Register 7 (R/W)
264
Address
Address
0x80065
0x80066
15:3
15:3
Bit
Bit
2
1
0
2
1
0
FRM_R_COSDTHI Receive Signaling Change of State FIFO Depth Threshold
FRM_R_COSTTHI Receive Signaling Change of State FIFO Timer Threshold
R_COSDTHM
FRM_R_COSOFI Receive Signaling Change of State FIFO Overflow Inter-
R_COSTTHM
R_COSOFM
Name
FRM_
FRM_
FRM_
Name
—
—
Reserved. Reads 0.
Receive Signaling Change of State FIFO Depth Threshold
Overflow Interrupt Mask. The corresponding interrupt status bit
will cause a processor interrupt if this bit is set to 0. The corre-
sponding interrupt status bit will be masked from causing a pro-
cessor interrupt if this bit is set to 1.
Receive Signaling Change of State FIFO Timer Threshold
Interrupt Mask. The corresponding interrupt status bit will cause
a processor interrupt if this bit is set to 0. The corresponding
interrupt status bit will be masked from causing a processor inter-
rupt if this bit is set to 1.
Receive Signaling Change of State FIFO Overflow Interrupt
Mask. The corresponding interrupt status bit will cause a proces-
sor interrupt if this bit is set to 0. The corresponding interrupt sta-
tus bit will be masked from causing a processor interrupt if this bit
is set to 1.
Reserved. Reads 0.
Overflow Interrupt. This interrupt status bit will be set when
the programmed threshold for the FIFO capacity has been
exceeded. This interrupt bit can be reset based on a clear-on-
read protocol, which is provisioned in the Super Mapper global
registers.
Interrupt. This interrupt status bit will be set when the pro-
grammed interrupt timer has expired and there are valid entries
in the FIFO to be processed. This interrupt bit can be reset
based on a clear-on-read protocol, which is provisioned in the
Super Mapper global registers.
rupt. This interrupt status bit will be set when the signaling
change of state FIFO overflows. The contents of the FIFO will
be lost and programmed threshold for the FIFO capacity has
been exceeded. This interrupt bit can be reset based on a
clear-on-read protocol, which is provisioned in the Super Map-
per global registers.
(continued)
Function
Function
Agere Systems Inc.
May 2001
Default
Reset
Default
Reset
0
1
1
1
0
0
0
0