tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 477

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description
Contents
Figures
Figure 52. Switching Application of the Super Mapper......................................................................................... 479
Figure 53. Super Mapper Switching Configuration ............................................................................................... 480
Figure 54. Super Mapper Switching Mode for Framer in DS0 Interface (Parallel or Serial) Configuration
Figure 55. Transport Application of the Super Mapper......................................................................................... 482
Figure 56. Super Mapper Transport Configuration ............................................................................................... 483
Figure 57. Super Mapper Transport (with Intrusive Performance Monitoring) Mode
Figure 58. DS1 Transparent Frame Structure ...................................................................................................... 486
Figure 59. CEPT Transparent Frame Structure ................................................................................................... 487
Figure 60. HG Alignment Algorithm ...................................................................................................................... 497
Figure 61. Rx Data Link Block Diagram ............................................................................................................... 511
Figure 62. Stack Available and Stack Ready Bit Formatting ................................................................................ 512
Figure 63. Tx Data Link Block Diagram................................................................................................................ 516
Figure 64. Receive HDLC Block Diagram ............................................................................................................ 519
Figure 65. Transmit HDLC FIFO Block Diagram .................................................................................................. 520
Figure 66. Framer PLL ......................................................................................................................................... 522
Figure 67. Framer Block Transmit Path Timing Selection .................................................................................... 523
Figure 68. System Loopbacks .............................................................................................................................. 525
Figure 69. CHI Mode of the Transmit System Interface ....................................................................................... 526
Figure 70. Nominal Concentration Highway Interface Timing .............................................................................. 527
Figure 71. CHIDTS Mode Concentration Highway Interface Timing .................................................................... 528
Figure 72. Associated Signaling Mode Concentration Highway Interface Timing ................................................ 529
Figure 73. TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS = 0 (CEX = 3 and CER = 4,
Figure 74. CHI TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS = 1
Figure 75. Parallel Bus System Interface Mode of the Transmit System Interface .............................................. 532
Figure 76. Parallel Bus System Interface Turnaround Timing .............................................................................. 536
Figure 77. Signals (6-Pin Mode) ........................................................................................................................... 537
Figure 78. Signals (8-Pin Mode) ........................................................................................................................... 537
Figure 79. Network Serial Multiplexed Interface (Single Octet)............................................................................ 538
Figure 80. Network Serial Multiplexed Interface (Multiple Octets)........................................................................ 539
Agere Systems Inc.
21.27 Serial Multiplex Interface ........................................................................................................................ 536
21.28 Superframer Host Interface .................................................................................................................... 540
21.29 Superframer Register Addressing .......................................................................................................... 541
21.26.16 The Parallel Bus System Interface Mode ................................................................................ 532
21.26.17 Distributed Stuffing: DS1 ......................................................................................................... 533
21.26.18 Distributed Stuffing: E1 ............................................................................................................ 535
21.26.19 Drive to 3-State and 3-State to Drive Timing ........................................................................... 536
21.27.1 Signals (6-Pin Mode) ................................................................................................................. 537
21.27.2 Signals (8-Pin Mode) ................................................................................................................. 537
21.27.3 Timing Diagrams ....................................................................................................................... 538
21.27.4 Time-Slot Sequencing ............................................................................................................... 539
21.27.5 Timing Between Transmit and Receive ..................................................................................... 539
21.28.1 Superframer Register Addressing ............................................................................................. 540
21.29.1 Per Link Register Sections in Table 609 ................................................................................... 542
Respectively) ....................................................................................................................................... 531
(CEX = 3 and CER = 6, Respectively) ................................................................................................ 532
(The Optional Byte-Synchronous VT Mapping Path Is Shown) .......................................................... 481
(The Optional Byte-Synchronous VT Mapping Path Is Shown) .......................................................... 484
Table of Contents
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
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(continued)
TMXF28155/51 Super Mapper
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