tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 578

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
24 Test-Pattern Generation/Detection Functional Description
The transmitted Sa bits (designated as spares in G.704) are a continuous repeat of the contents of the
TPG_E1SAx[4:8] registers
to Table 5B in G.704, the E1SA1[4:8] bits are the SA bits in SMF 1 and 9, the E1SA2[4:8] bits are the Sa bits in
SMF 3 and 11, etc.
24.5.7 DS2 TPG Framing
The DS2 generator provides an unframed DS2 rate test sequence.
24.5.8 DS3 TPG Framing
For DS3 test signals, the TPG provides a raw PN sequence on TPG_DATA[5] using the enabled clock.
24.5.9 Line Encoding/Decoding
For DS1 and E1 test signals, the TPG may be provisioned to transmit and receive AMI coded signals
TPG_TPM_CODEx
coded. If coding is selected, it is active for both transmit and receive paths. For coded signals, the DATA inputs/out-
puts become the positive rails and the sync inputs/outputs become the negative rails.
24.5.10 TPG Test-Pattern Sequences
The test-pattern bit sequence generated on the nonidle TPG_DATAx lines is determined by the TPG_SEQm[2:0]
(Table
and 5 = DS3). One of seven sequences presently may be selected for transmission within the framed or unframed
test pattern on the corresponding even TPG_DATAx lines (the odd lines are connected to idle generators). Each
datastream also has an associated clock TPG_CLKx and frame-sync signal TPG_FSx (x even, except DS2).
TPG_SEQm[2:0] values are described in the following table:
The polarity of the output data stream may also be provisioned to normal TPG_TPINVx = 0
and 510) or inverted TPG_TPINVx = 1.
Table 625. TPG Test-Pattern Sequences
578
TPG_SEQm
000
001
010
011
100
101
110
111
507, 508, 509, and 510) register values, where m is the rate index (0 = DS1, 2 = E1, 4 = DS2,
PRBS15. 2
shift register whose 14th and 15th stages are added and fed back to the first stage. The output of
the last stage is inverted (which yields a sequence with up to 15 consecutive zeros) to produce
the transmitted sequence.
PRBS20. 2
17th and 20th stages are added and fed back to the first stage. The transmitted test sequence is
normally the noninverted output of the last (20th) stage.
QRSS. 2
erated by a 20-stage shift register whose 17th and 20th stages are added and fed back to the first
stage. The transmitted test sequence is normally the non-inverted output of the last (20th) stage,
but the test sequence is forced high if the outputs of stages 6 through 19 are low.
PRBS23. 2
ALT_01. Alternating sequence of ones and zeros.
ALL_ONES. All-ones sequence.
Note: If unframed, an AIS signal is generated.
Reserved.
User-Defined. Continuously repeating 16-bit pattern from TPG_USER[15:0]
(Table 507
20
(Table 505
– 1 PN sequence with zero-suppression as specified in O.150. This sequence is gen-
15
20
23
– 1 PN sequence specified in O.150. This sequence is generated by a 15-stage
– 1 PN sequence. This sequence is generated by a 20-stage shift register whose
– 1 PN sequence.
and
Table
and
508). The signals can be uncoded, B8ZS coded, HDB3 coded, or AMI
Table
506). These bits are synchronized to the CRC-4 frame. Referring
Test Pattern
(continued)
(Table
(Table
Agere Systems Inc.
507, 508, 509,
511).
May 2001