tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 94

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers
Table 93. TMUX_RHS_CTL, Receive High-speed Control Parameters (R/W)
Table 94. TMUX_RLS_BITBLK_CTL, Receive Low-speed Control Parameters (R/W)
94
Address
Address
0x4001A
0x40019
15:9
Bit
8:7
15:4
Bit
6
5
4
3
2
1
0
3
2
1
0
TMUX_RCV_SS_EXP[1:0] Expected Receive Pointer Size Bits Value.
TMUX_LOSEXT_LEVEL Controls External LOSEXT Polarity.
TMUX_RCV_SS_ENB
TMUX_RPSMUXSEL1
TMUX_THS2RHSLB
TMUX_BITBLKM1
TMUX_BITBLKG1
TMUX_BITBLKB3
TMUX_BITBLKB2
TMUX_BITBLKB1
TMUX_RHSDSCR
(continued)
Name
Name
—
—
—
Reserved.
0 = active-low. 1 = active-high.
Receive Protection Switch Control. Control bit,
when set to a logic 1, causes the receive protec-
tion switch data and clock inputs to be selected;
otherwise, the normal receive high-speed data
input is selected.
Transmit High-speed to Receive High-speed
Loopback Control. Control bit, when set to a
logic 1, causes the transmit output STS-3/STM-1
(AU-4) signal to be looped back to the receive
input; otherwise, the loopback is disabled.
Receive High-speed Descramble Enable. Con-
trol bit, when set to a logic 1, causes the input
STS-3/STM-1 (AU-4) signal to be descrambled;
otherwise, the signal is not descrambled.
Reserved.
Expected value of incoming pointer SS bits.
Receive Size Bits Enable. Control bit, when set to
a logic 0, causes the received size bits to be
ignored by the pointer interpreter; otherwise, the
received size bits must equal the expected size bits
or the received pointer value will be invalid.
Reserved.
Receive Bit/Block Error Count Control. Control
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
Receive Bit/Block Error Count Control. Control
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
Receive Bit/Block Error Count Control. Control
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
Receive Bit/Block Error Count Control. Control
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
Receive Bit/Block Error Count Control. Control
bit, when set to a logic 0, causes the receive error
counter to count bit errors; otherwise, count block
errors (a block equals one frame).
Function
Function
Agere Systems Inc.
Reset Default
Reset Default
May 2001
0x000
0x00
00
0
0
0
0
0
0
0
0
0
0
0