tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 3

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

May 2001
1 Features
Agere Systems Inc.
Alarm reporting and performance monitoring per
AT&T, ANSI , ITU-T, and ETSI standards.
Facility data link features:
HDLC features:
System interfaces:
— HDLC or transparent access for either ESF or
— Register/stack access for SLC -96 transmit and re-
— Extended superframe (ESF): automatic transmis-
— Register/stack access for all CEPT Sa-bits trans-
— HDLC or transparent mode.
— Programmable logical channel assignment: any
— 64 logical channels in both transmit and receive di-
— Maximum channel data rate: 64 kbits/s.
— Minimum channel data rate: 4 kbits/s (DS1-FDL or
— 128-byte FIFO per channel in both transmit and re-
— Tx to Rx loopback supported.
— Concentration highway interface: Single clock and
— Parallel system bus interface at 19.44 MHz for
— Time-division multiplex data rate serial interface at
— Network serial multiplexed interface minimal pin
DDS + FDL frame formats.
ceive data.
sion of the ESF performance report messages
(PRM). Automatic transmission of the ANSI
T1.403 ESF performance report messages. Auto-
matic detection and transmission of the ANSI
T1.403 ESF FDL bit-oriented codes.
mit and receive data.
time slot, any bit for ISDN D-channel, also inserts/
extracts C-channels for V5.1, V5.2 interfaces.
rection (any framing format).
E1 Sa bit).
ceive direction.
frame sync signals; programmable clock rates at
2.048 MHz, 4.096 MHz, 8.192 MHz, and
16.384 MHz; programmable data rates at 2.048
Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s; programmable
clock edges and bit/byte offsets.
data and signaling: single clock and frame sync
signals.
1.544 MHz or 2.048 MHz. Twenty-eight receive
data, clock, and frame sync signals. Twenty-eight
transmit data signals with a global clock and frame
sync.
count serial interface at 51.84 MHz optimized for
data and IMA applications.
(continued)
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
1.11 System Test and Maintenance
Microprocessor Interface
Chip Testing and Maintenance
Interface to Other
Seamless interface to the following
devices:
* IEEE is a registered trademark of the Institute of Electrical and
Electronics Engineers, Inc.
A variety of loopback modes implemented on
SONET/SDH side as well as on framer level.
Built-in test pattern generator and monitor config-
urable for simultaneously testing E1, DS1, DS2, and
DS3 (one channel each).
20-bit address and 16-bit data interface with 16 MHz
to 66 MHz read and write access.
Compatible with most industry-standard processors.
IEEE * 1149.1 JTAG boundary scan.
TADM042G5.
Agere
ME Devices
Agere Systems’
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