tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 580

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
24 Test-Pattern Generation/Detection Functional Description
A TPM_OOFxD
nal. The TPM_OOFxD signal is reset to 0 based on the SMPR_COR_COW
Register (RW) on pag
any microprocessor read of the event or delta register. If SMPR_COR_COW is 0, each event or delta signal must
be written with a 1 to clear it. The TPM_OOFxD signal, if asserted, will generate an interrupt unless the corre-
sponding mask bit TPM_OOFxDM
Also, synchronization is checked for the designated test patterns. If the TPM monitor detects 32 consecutive
matches in its input sequence, the corresponding TPM_OOSx
four or more consecutive mismatches in the input sequence, the corresponding TPM_OOSx is set. The
TPM_OOSx condition (status) signals default to 1, indicating an out-of-sync condition.
A TPM_OOSxD
nal. The TPM_OOSxD signal is reset to 0 based on the SMPR_COR_COW global control signal: if
SMPR_COR_COW is set, delta signals are cleared on any microprocessor read of the delta register. If
SMPR_COR_COW is 0, each delta signal must be written with a 1 to clear it. The TPM_OOSxD signal, if asserted,
will generate an interrupt unless the corresponding mask bit TPM_OOSxDM
DS2 (x = 4). The DS2 monitor checks for synchronization of the unframed PRBS signals, and for bit errors as
above.
DS3 (x = 5). The DS3 monitor checks for synchronization of the unframed PRBS signals, and for bit errors as
above.
24.6.2 TPM Error Detection and Counting
TPM Bit Errors. While in sync, each data monitor detects and counts the number of times that the input sequence
differs from the expected sequence in a 16-bit counter (one per rate). Detection of a bit error causes the TPM to
latch a 1 into the TPM_BEREx
SMPR_COR_COW global control signal (if set, the event is automatically cleared on read, otherwise a 1 must be
written to the TPM_BEREx register bit to clear it). If the interrupt is enabled (not masked) via TPM_BERMx
(Table
The error counters accumulate TPM_BEREx events in a set of active counters. The active counter values are
transferred to registers upon assertion of global control signal SMPR_PMRESET
Trigger Register (RW) on page66
registers called TPM_CNTx[15:0] (Tables 513, 514, 515, and 516). The active counters will roll over or saturate at
the terminal count depending on global control signal SMPR_SAT_ROLLOVER
Control Register (RW) on page68
is set; otherwise, the counter values are not affected by reads and instead must be cleared by explicit writes. The
global control signals SMPR_PMRESET, SMPR_SAT_ROLLOVER, and SMPR_COR_COW operate on all six test
channels; there are no separate controls per rate or mode.
TPM Framing Errors. Framing-bit errors TPM_FEREx
but not counted. The event is latched and may be used to trigger a (maskable) interrupt, or may be polled (the error
assertion will last between one and 24 frame intervals). The interrupt mask bit is called TPM_FERExM
The global control signal SMPR_COR_COW determines if the TPM_FEREx event is cleared on read or write.
TPM CRC Errors. Cyclic redundancy check (CRC) errors TPM_CRCEx
TPM_FRAMEx
super-frame (ESF) test patterns. CRC-4 errors are valid only for E1 multiframe test patterns. Each CRC error event
is latched and may be used to trigger a (maskable) interrupt, or may be polled (the error assertion will last between
1 and 24 frame intervals).
CRC-6 errors (DS1-ESF only) are detected via TPM_CRCE0. Interrupts are managed via TPM_CRCE0M
(Table
on page68
580
491) mask bits, then this event will trigger an interrupt.
495) bit. The global control signal SMPR_COR_COW
) determines if the TPM_CRCE0 event is cleared on read or write.
(Table 507
(Table
(Table
e68) global control signal: if SMPR_COR_COW is set, event or delta signals are cleared on
482) signal detects and latches delta events (changes or transitions) in the TPM_OOFx sig-
483) signal detects and latches delta events (changes or transitions) in the TPM_OOSx sig-
and
(Table
Table
). The counter values may be read via the microprocessor control interface via
). The counters will clear on read if the global control signal SMPR_COR_COW
(Table
508) is 1 but not counted. CRC-6 errors are valid only for DS1 extended
490) event register bit. Clearing of this latched event is determined by the
489) is set.
(Table
(Table 67, SMPR_GCR, Global Control Register (RW)
485) events are detected when TPM_FRAMEx is 1
(Table
497) is cleared. Similarly, if the TPM detects
(Table
(Table 67, SMPR_GCR, Global Control
(Table
488) are detected when
(Table 67, SMPR_GCR, Global
(Table 65, SMPR_GTR, Global
490) is set.
(continued)
Agere Systems Inc.
(Table
May 2001
492).