tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 540

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
8-Pin Mode. As in the 6-pin mode, the Super Mapper sends data and link information through the transmit signals.
However, in the 8-pin mode, it requests data through the extra transmit signals. The data is then expected to be
sent back for the same link number and time slot on the Super Mapper’s receive signals. As in the 6-pin mode, the
only requirement is that it receives data at a constant time interval.
21.28 Superframer Host Interface
21.28.1 Superframer Register Addressing
Table 608 summarizes the current number of global and per link/channel registers for each block.
Table 608. Current Number of Global and per Link/Channel Registers for Each Block
All of the block global registers will be combined with the top global register. Each block will receive a global select
and a per link/per channel select.
The block addressing is summarized below. An extra bit is used for future growth of global and link/channel regis-
ters.
Table 609
(0 selects link and global registers; 1 selects HDLC registers). When an HDLC channel is to be addressed, bits
B13—B8 indicate the HDLC channel numbers 0—63 (000000—111111), bit B7 indicates the transmit or receive
paths, and bits B3—B0 indicate the register number. When a link is selected, bits B13—B9 indicate the link num-
bers 1—28 (00001—11100), and bit B8 indicates the transmit and receive paths for the link. Bits B7—B0 indicate
the block and register number, as shown in Framer Addressing Map for the Global and Per Link/Channel Registers
of the Superframer,
a block using bits B7—B4, and selecting a register using bits B3—B0.
540
describes the addressing scheme. Bit 14 is used to indicate whether a link or HDLC channel is selected
RXP HDLC
TXP HDLC
RXP SYS
TXP SYS
RXP SIG
TXP SIG
RXP PM
TXP PM
RXP FF
RXP DL
RXP LC
TXP FF
TXP DL
TXP LC
Block
TOP
AR
Table 609 on page
541. Global registers are selected by setting B14—B9 = 000000, selecting
Global
15
15
1
0
0
0
5
1
6
6
0
0
1
1
0
0
(continued)
Per Link/Per Channel
19/0
19/0
41/0
36/0
0/0
2/0
2/0
2/0
3/0
2/0
0/8
0/8
9/0
9/0
1/0
1/0
Agere Systems Inc.
May 2001