tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 355

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

May 2001
16 Microprocessor Interface Functional Description
16.1 Introduction
The Super Mapper microprocessor interface consists of a 20-bit address and a 16-bit data bus. In addition, this
block contains global control and status registers. These registers include the summary of interrupt status of major
functional blocks and the control to enable them or power them down.
16.2 Features
16.3 Microprocessor Interface
This device is equipped with a generic 20-bit address/16-bit data microprocessor interface that allows operation
with most commercially available microprocessors. Device input pin MPMODE (pin AD17) is used to configure this
interface into one of two possible modes (synchronous or asynchronous). In synchronous mode (MPMODE = 1),
the microprocessor interface can operate at speeds from 16 MHz up to 66 MHz. In asynchronous mode
(MPMODE = 0), a 16 MHz to 66 MHz clock is required on the MPCLK (pin AE17) pin for proper operation.
Two parity detectors are provided for the microprocessor data bus, one for the higher-order byte and one for the
lower-order byte. The parity sense is programmed as even or odd with register bit SMPR_PARITY_EVEN_ODD
(Table 67 on page68
(Table 63 on page64
(Table 64 on page65
functional without parity supplied by the host processor.
The interrupt status from each of the major blocks, the automatic protection switch, and the microprocessor data
bus parity are summarized in
the interrupt mask register, see
Agere Systems Inc.
20-bit address/16-bit data bus microprocessor interface.
Synchronous (16 MHz to 66 MHz)/asynchronous microprocessor interface modes.
Microprocessor data bus parity monitoring.
Summary of interrupts from major functional blocks/maskable.
Separate device interrupt outputs for automatic protection switch and the Super Mapper global interrupt.
Global configuration of network performance monitoring counters operation.
Global software resets.
Global enabling and powering down of major functional blocks.
Miscellaneous global configuration and control.
). The composite status of both parity detectors is indicated in register bit SMPR_PARITY_IS
). The interrupt from this status indicator may be masked with register bit SMPR_PARITY_IM
). A bad parity event does not inhibit a data transfer. The microprocessor interface is fully
Table 63 on page
Table 64 on page65
64. Each interrupt is maskable with the complementary bit set in
.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
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