tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 555

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tmxf28155

Manufacturer Part Number
tmxf28155
Description
Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
Manufacturer
ETC-unknow
Datasheet

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Preliminary Data Sheet
May 2001
22 Cross Connect (XC) Block Functional Description
22.6.6 Framer System Interface—PSB
The framer system interface is configured for the parallel system bus as depicted in
gram bit XC_SI_CHI = 1 to select the PSB mode, and bit XC_SYNC_FOR_DATA = 1 to allow the connecting of
transmit system data outputs to the LINETXSYNC[1—29] pins. The programming of the XC_CHI_MODE[1—7][1:0]
bits is not required.
The PSB configuration is completed by programming appropriate source IDs into the XC_RS_D[1—28][7:0]
(Table
XC_PINS_SRC[1—14]
22.6.7 Framer System Interface—CHI
The framer system interface is configured for CHI operation as shown in
XC_SI_CHI = 0
connecting of transmit system data outputs to the LINETXSYNC[1—29] pins.
The concentration highway interface can operate at data rates of 2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s.
The CHI interface allows a single system interface to support combining 2 or 4 DS1/E1s at 4.096 Mbits/s and
8.192 Mbits/s, respectively. Therefore, the 28-channel framer block may result in as many as 28 CHIs or as few as
7 combined CHIs or a mix as determined by the specific needs of the application.
Agere Systems Inc.
457) and XC_SYNC[1—29]
LINETXSYNC[16—13]
LINERXSYNC[16—1]
LINETXSYNC[4—1]
EXTERNAL I/O
LINERXSYNC29
LINETXSYNC29
LINERXDATA29
LINERXCLK29
LINETXCLK29
AS PSB
(Table
Figure 86. Framer System Interface—Parallel System Bus (PSB)
449) to select the CHI mode, and bit XC_SYNC_FOR_DATA = 1
(Table
465) XC1 crosspoint configuration registers.
XC_CHI_MODE[1—7][1:0] = 00
XC1
(Table
XC_SI_CHI = 1
465) bytes of the XC_FRS_SRC[1—14]
XC
XC_SYNC_FOR_DATA = 1
XC_RS_D[1—28][7:0]
XC_SYNC[1—29][7:0]
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Figure 87 on page556
(continued)
TMXF28155/51 Super Mapper
(Table
FRAMER SYSTEM INTERFACE
Figure 86 on page555
TS_D[16—1]
RS_D[16—1]
TS_GCLK
TS_GFS
RS_GCLK
RS_GFS
RS_GTCLK
FRM_TS/FRM_RS
(Table
457) and
449) to allow the
. Program bit
. Pro-
5-9185(F)r.2
555

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