tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 68

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
7 Microprocessor Interface and Global Control and Status Registers
Table 67. SMPR_GCR, Global Control Register (RW)
68
Address
0x0000F 15:10
9:8
7:5
Bit
4
3
2
1
0
SMPR_PARITY_EVEN_ODD Even or Odd Parity Indication on the Microproces-
SMPR_FXD_STFF_DEFLT
SMPR_SAT_ROLLOVER
SMPR_PMMODE[1:0]
SMPR_OH_DEFLT
SMPR_COR_COW
Name
—
—
Reserved.
Performance Monitor Mode:
00 = PMRST comes from external pin.
10 = PMRST comes from external pin.
01 = PMRST comes from internal 1 second counter.
Note:
11 = PMRST is software controlled using the
Reserved.
sor Data Bus. This bit controls the parity setting and
checking on the microprocessor data bus:
0 = Even parity on microprocessor byte data/parity bus.
1 = Odd parity on microprocessor byte data/parity bus.
Overhead Default. This bit controls the filling of the
unused overhead bytes:
0 = Filling the unused overhead bits with 0.
1 = Filling the unused overhead bits with 1.
Fixed Stuff Default. This bit control the filling of the
fixed stuff bytes:
0 = Filling the fixed stuff bytes with 0.
1 = Filling the fixed stuff bytes with 1.
Clear On Read or Clear On Write. This bit controls the
way clearing is performed on all delta and event bits in
all registers:
0 = The delta and event bit is cleared by writing a 1 to it.
Note: The clear-on-write (COW) feature does not apply
1 = The delta and event bit is cleared when a micropro-
Saturate or Rollover. This bit controls if error counters
hold their values or rollover when they reach their maxi-
mum values.
0 = Error counters rollover when reaching maximum val-
1 = Error counters hold their values when reaching max-
cessor read is performed on this delta and event bit.
ues.
imum values.
SMPR_PMREST register bit 8
page
Please see
to all registers in the 28-channel framer block.
The only framer block register that has COW is
transmit FDL link register 8 (address 0x8LTD7).
All other registers in the framer block are only
clear-on-read.
66).
Table 72
Function
and
Table
(Table 65 on
73.
Agere Systems Inc.
(continued)
May 2001
Default
0x0000
Reset