tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 444

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
19 VT/TU Mapper Functional Description
Table 561. RDI-V, RFI-V, and REI-V Automatic Generation
444
When operating in UPSR mode VT_V5_INS[1—28] = 1, REI-V is set to the value in the received LOPOH serial
access channel storage when enabled by bit, VT_REI_EN[1—28] =1
mode VT_V5_INS[1—28] = 0, REI-V is set to 1 for any detected BIP-2 errors in the corresponding received VT
when enabled by bit, VT_REI_EN = 1. Otherwise, the REI-V bit is set to 0.
RFI-V is supported. Manual control of the RFI-V bit is enabled with bit VT_RFI_EN[1—28] = 1
RFI-V bit is programmed with the value of bit VT_RFI_INS[1—28]
operating in UPSR mode VT_V5_INS[1—28] = 1, RFI-V is set to the value in the received LOPOH serial access
channel storage. Otherwise, RFI-V is automatically generated and inserted as defined in
When operating in byte synchronous mode, RFI-V is also based on the incoming DS1 RAI from the framer.
One bit RDI-V is supported when bit VT_TX_ERDI_EN[1—28] = 0
enabled with bit VT_RDI_EN[1—28] =1
VT_RDI_INS[1—28]
VT_V5_INS[1—28] = 1
age. Otherwise, RDI-V is automatically generated and inserted as defined in
Enhanced RDI will be supported when bit VT_TX_ERDI_EN[1—28] = 1. Manual control of the ERDI bits 5, 6,
and 7 of the Z7 byte is enabled with bit VT_ERDI_EN[1—28] = 1
and 7 of the Z7 byte are programed with the value of bits VT_ERDI_INS[1—28][2:0]
When VT_ERDI_EN[1—28] = 0 and operating in UPSR mode VT_V5_INS[1—28] = 1
to the value in the received LOPOH serial access channel storage. Otherwise, bits 5, 6, and 7 of the Z7 byte are
automatically generated and inserted as defined in
(V5 bit 8)
RDI-V
RDI-V
REI-V
RFI-V
0
1
0
1
0
1
0
0
1
1
No BIP-2 errors detected.
BIP-2 errors detected.
No alarms.
AIS-V, LOP-V, UNEQ-V, PLM-V or automatic AIS detected from SPEMPR.
No alarms.
AIS-V, LOP-V, UNEQ-V, or TIM-V.
(Z7 bit 5)
RDI-V
0
0
1
1
(Table
(Table
Enhanced Remote Defect Indication ( Bellcore GR-253)
200). When VT_RDI_EN[1—28] = 0 and operating in UPSR mode
199), RDI-V is set to the value in the received LOPOH serial access channel stor-
(Z7 bit 6)
RDI-V
0
1
0
1
One Bit Remote Failure Indication
One Bit Remote Defect Indication
(Table
Remote Error Indication
(Z7 bit 7)
RDI-V
198). The RDI_V bit is programed with the value of bit
1
0
1
0
Table 561
Anomaly/defect.
Anomaly/defect.
Anomaly/defect.
(continued)
No defects.
PLM-V (VT payload mismatch).
AIS-V or LOP-V.
UNEQUIP-V or TIM-V.
below.
(Table
(Table
(Table
(Table
198). The ERDI bits, in bit positions 5, 6,
200). When VT_RFI_EN[1—28] = 0 and
198). Manual control of the RDI-V bit is
198). When operating in normal
Anomaly/defect
Table 561
(Table
(Table
below.
Table 561 on page
200), respectively.
199), ERDI-V is set
Agere Systems Inc.
(Table
May 2001
198). The
444.