tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 78

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers
Table 80. TMUX_TX_DLT, Delta/Event (COR/COW)
Table 81. TMUX_RPS_DLT, Delta/Event (COR/COW)
78
Address
Address
0x40004
0x40005
15:7
15:6
Bit
6:4
Bit
3
2
1
0
5
4
3
2
1
0
TMUX_TLSPARE[3:1] Transmit Low-speed Parity Error Event (Input Port Num-
TMUX_RPSILOCD Receive Protection High-speed Loss of Input Clock
TMUX_RPSOOFD
TMUX_RPSLREIE
TMUX_TPOAC_PE
TMUX_RPSLOFD
TMUX_TTOAC_PE
TMUX_THSILOCD
TMUX_THSILOFD
TMUX_RPSB2E
(continued)
Name
Name
—
—
—
Reserved.
Receive Protection High-speed Loss of Frame Delta. This
delta bit indicates a change in state of TMUX_RPSLOF
(Table
Receive Protection High-speed Out of Frame Delta. This
delta bit indicates a change in state of TMUX_RPSOOF
(Table
Delta. This delta bit indicates a change in state of the
TMUX_RPSILOC
TMUX_RPSILOCM
Receive Protection High-speed B2 Error Event. This event
bit indicates a B2 error was detected in the receive protection
input. The mask bit is TMUX_RPSB2M
Receive Protection High-speed Line REI Event. This
event bit indicates a line REI error was detected in the
receive protection input. The mask bit is TMUX_RPSLREIM
(Table
Reserved.
Reserved.
ber). This event bit indicates a byte transfer parity error was
detected on the respective STS-1/AU-3 input. The mask bits
are TMUX_TLSPARM[3:1]
Transmit Path Overhead Access Channel (TPOAC) Par-
ity Error Event. This event bit indicates a parity error was
detected on the incoming transmit path overhead access
channel. The mask bit is TMUX_TPOAC_PM
Transmit Transport Overhead Access Channel (TTOAC)
Parity Error Event. This event bit indicates a parity error
was detected on the incoming transmit transport overhead
access channel. The mask bit is TMUX_TTOAC_PM
(Table
Transmit High-speed Input Loss of Frame Delta. This
delta bit indicates a change of state for the transmit loss of
frame bit TMUX_THSILOF
TMUX_THSILOFM
Transmit High-speed Input Loss of Clock Delta. This
delta bit indicates a change of state for the transmit loss of
high-speed clock bit TMUX_THSILOC
bit is TMUX_THSILOCM
90). The mask bit is TMUX_RPSLOFM
90). The mask bit is TMUX_RPSOOFM
85).
84).
(Table
(Table
(Table
90) state bit. The mask bit is
Function
Function
(Table
85).
84).
(Table
(Table
84).
84).
89). The mask bit is
(Table
(Table
89). The mask
(Table
85).
(Table
(Table
Agere Systems Inc.
85).
85).
84).
May 2001
Default
Default
Reset
0x000
Reset
0x000
0
0
0
0
0
0
0
0
0
0
0