tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 496

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
21.13 Receive Signaling Interrupts
There are three interrupts which are maintained in the receive signaling processor, which are located in
FRM_SGR7, receive signaling global register 7 (R/W),
tus of the change of signaling state FIFO. These interrupt bits can be reset based on a clear-on-read protocol,
which is provisioned in the Super Mapper global registers.
There are mask bits associated with each of the three interrupt status bits which are located in FRM_SGR7,
receive signaling global register 7 (R/W).
21.13.1 Maintenance of the Change of Signaling State FIFO Status Bits
There is one bit which reflects the status of the change of signaling state FIFO. The location of this status bit is in
FRM_SGR5, receive signaling global register 5 (RO),
21.13.2 Maintenance of Handling Group Related Status Bits
There are three bits which reflect the status of the handling groups extracted from the VT mapper interface. There
are four handling groups on each link therefore there will be three copies of the following bits for each link. The
location of these status bits are in FRM_RSLR33, Receive Signaling Link Register 33 (R/W),
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Threshold overflow interrupt. This bit is set to 1 when the programmed threshold for the FIFO capacity has been
exceeded.
Interrupt timer interrupt. This bit is set to 1 when the programmed interrupt timer has expired and there are valid
entries in the FIFO to be processed.
FIFO overflow interrupt. This bit is set to 1 when the FIFO overflows.
FIFO depth threshold overflow status. This bit is set to 1 when the programmed threshold for the FIFO capacity
has been exceeded.
Loss of HG alignment. Alignment uses the 0101010 . . . framing pattern and follows the alignment algorithm
shown in
AIS detection within each handling group (AIS detection 48 consecutive ones, AIS loss any two zeros).
RDI detection within each handling group (RDI detection is the presence of three consecutive zeros in the Sp bit
position).
269.
Figure 60 on page497
.
Table 363 on page263
Table 365 on page264
(continued)
.
. The three interrupts reflect the sta-
Table 374 on
Agere Systems Inc.
May 2001