tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 55

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
5 Timing Characteristics
MPCLK
ADDR [19:0] The address will be available throughout the entire cycle.
DATA[15:0]
RWN (Input) The read (H) write (L) signal is always high except during a write cycle.
CSN (Input) Chip select is an active-low signal.
DTN (Output) Data transfer acknowledge is active-low for one clock and then driven high before entering a high-
ADSN (Input) Address strobe is active-low. ADSN must be 1 MPCLK clock period wide.
Table 51. Microprocessor Interface Synchronous Write Cycle Specifications
(See Figure 14 on page 54
Agere Systems Inc.
T
Symbol
t
t
t
ADSNVDTF
t
ADSNVS
DTNVPD
DTNIPD
CSNVS
T
t
t
t
AIPD
APD
WS
CLK
(66 MHz MAX)
Figure 15. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1)
MPCLK 16 MHz Min—66 MHz Max Frequency
ADDR, RWN, DATA (write) Valid to MPCLK
MPCLK to ADDR, RWN, DATA, CSN (write) Invalid
CSN Valid to MPCLK
ADSN Valid to MPCLK
MPCLK to ADSN Invalid
MPCLK to DTN Valid
MPCLK to DTN Invalid
ADSN Valid to DT Falling
MPCLK
DATA[15:0]
ADDR[9:0]
(OUTPUT)
16 MHz minimum to 66 MHz maximum frequency.
Data will be available during cycle T1.
impedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state
term.) DTN will become 3-stated when CSN is high. Typically DTN is active 4 or 5 MPCLK cycles
after ADSN is low.
ADSN
RWN
CSN
DTN
HIGH Z
for the timing diagram.)
tADSNSU
tCSNSU
tAVS
Parameter
(continued)
T0
T1
tSNIPD
T2
tADSNVDTF
Tn – 4
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Tn – 3
Setup (ns)
(Min)
tDVPD
3.5
3.5
5.5
—
—
—
—
—
—
Tn – 2 Tn – 1
TMXF28155/51 Super Mapper
Hold (ns)
(Min)
—
—
—
—
0
5
0
0
5
Tn
tAPD
tDIPD
Delay (ns)
tDAIPD
(Max)
1000
16
16
—
—
—
—
—
—
HIGH Z
Delay (ns)
(Min)
5-7660(F).a
—
—
—
—
—
—
—
4
4
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