tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 381

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
17 TMUX Functional Description
Any change to F3 byte monitor registers is reported in TMUX_RF3MOND[1—3]
TMUX_RF3MONM[1—3]
The TMUX also maintains a history of the previous valid F3 byte in TMUX_F3MON1[1—3][7:0]
page
out of frame state.
K3 Byte Monitor. The TMUX monitors the K3 byte for each STS-1/STM-1. The K3 byte(s) are stored in
TMUX_K3MON[1—3][7:0]
TMUX_CNTDK3[3:0]
STS-1/STM-1. That is, the 8-bit pattern must be identical for a number of frames prior to updating the K3 register.
Any change to K3 monitor registers is reported in TMUX_RK3MOND[1—3]
TMUX_RK3MONM[1—3]
upon the transition of the framer into the out of frame state.
N1 Byte Monitor. The TMUX monitors the N1 byte for each STS-1/STM-1. The N1 byte(s) are stored in
TMUX_N1MON[1—3][7:0]
the value in TMUX_CNTDN1[3:0]
lar STS-1/STM-1. That is, the 8-bit pattern must be identical for a number of frames prior to updating the N1 regis-
ter. Any change to N1 monitor registers will be reported in TMUX_RN1MOND[1—3]
bits, TMUX_RN1MONM[1—3]
0 upon the transition of the framer into the out of frame state.
Signal Degrade BER Algorithm. A signal degrade state in register bit TMUX_RHSSD
change of state indication is reported in register bit, TMUX_RHSSDD
interrupt mask bit, TMUX_RHSSDM
B2 errors, determined by the value of TMUX_SDB1B2SEL
pendent signal degrade function as well in TMUX_RSDB3[1—3]
Declaring the signal degrade state requires the definition of two measurement windows, a monitoring block consist-
ing of a number of frames in TMUX_SDNSSET[18:0]
ing of a number of monitoring blocks in TMUX_SDBSET[11:0]
number of bit errors equals or exceeds a threshold set in TMUX_SDLSET[3:0]
declared when a number of bad monitoring blocks equals or exceeds the threshold in TMUX_SDMSET[7:0]
(Table
Clearing the signal degrade state requires the definition of two measurement windows, a monitoring block consist-
ing of a number of frames in TMUX_SDNSCLEAR[18:0]
number of monitoring blocks in TMUX_SDBCLEAR[11:0]
ber of bit errors is less than a threshold set in TMUX_SDLCLEAR[3:0]
a number of good monitoring blocks equals or exceeds the threshold in TMUX_SDMCLEAR[7:0]
measurement interval.
The set parameters are used when the signal degrade state is clear, and the clear parameters are used when the
signal degrade state is declared.
The signal degrade state may be forced to the declared state with TMUX_SDSET
to the cleared state with TMUX_SDCLEAR
rithm into the failed state or normal state, respectively.
The algorithm described above can detect bit error rates from 1 x 10
Agere Systems Inc.
101). The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the
526) for the measurement interval.
(Table 99 on page99
(Table 87 on page89
(Table 87 on page89
(Table
(Table 104 on page101
(Table 87 on page89
104). Each register will be updated after a number determined by the value in
(Table 99 on page
(Table 87 on page
) of consecutive frames of identical K3[7:0] for that particular
(Table
(continued)
).
). The continuous N-times detection counter(s) will be reset to 0
78). One shot signal must be provided to force the BER algo-
). Each register will be updated after a number determined by
). The continuous N-times detection counter(s) will be reset to
99) of consecutive frames of identical N1[7:0] for that particu-
(Table 120 on page116
89). This bit error rate algorithm can operate on either B1 or
(Table
(Table
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(Table 95 on page95
(Table
120) and a measurement interval consisting of a
120). A block is determined good when the num-
(Table 92 on page92
–3
120). A block is determined bad when the
(Table
(Table 82, starting on page79
to 1 x 10
(Table
120). Signal degrade is cleared when
TMXF28155/51 Super Mapper
) and a measurement interval consist-
(Table
(Table
–9
). Each B3 monitor has an inde-
(Table 78 on page
.
83), with interrupt mask bits,
(Table
120). Signal degrade is
83), with interrupt mask bits,
).
(Table 91 on page
83), with interrupt mask
(Table 104 on
(Table
77) and forced
), with the
120) for the
92) and
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