tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 519

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description
21.24.6 HDLC Mode
The receive queue manager forms a status of frame (SF) word for each HDLC frame and stores the SF word in the
receive HDLC FIFO after the last data byte of the associated frame. HDLC frames that include the payload and the
frame check sequence (FCS) bytes and consists of n bytes will have n + 1 bytes stored in the receive FIFO. The
FCS bytes of the received HDLC frame are stored into the receive FIFO.
21.24.7 Receive HDLC Transparent Mode
The receive FIFO receives data from the receive framer and directly stores this data information bit-for-bit, least
significant bit first.
If the FRM_MODE[3:0]
load data only after the matched pattern has been detected. The search for the match character is in a sliding win-
dow fashion and data is aligned accordingly. The octet is aligned relative to the first HDLC clock after frame align-
ment is established. The match character and all subsequent bytes are placed into the receive FIFO. A receive
reset command causes the receive to realign to the match character if enabled.
21.24.8 Receive HDLC
Data is presented to the TDM to channel conversion block from the TDM bus (see
determines which, if any, channel the data belongs to. When data is found that belongs to a channel, it is sent to the
HDLC serial to parallel block. This block buffers up bits into bytes and does HDLC processing on channels so pro-
grammed. When a valid byte of data (or status) has been grouped together for a specific channel, that data is then
sent to the FIFOs interrupt block. Here, the data is further buffered in separate FIFOs for each channel where data
can be read by the microprocessor.
21.24.9 Receive HDLC Features
Agere Systems Inc.
In transparent mode, bits are simply gathered into bytes with the option of waiting for an initial provisionable 8-bit
pattern to be detected before starting.
In HDLC mode, incoming data is correctly formatted and packetized according to the HDLC standard.
In HDLC mode, aborted packets, idle status, and CRC errors are checked for and reported.
INTERNAL
TDM BUS
P CNTL
P ADDR
P DATA
(Table
CONVERSION
CHANNEL
TDM TO
422) and FRM_MATCH[7:0]
Figure 64. Receive HDLC Block Diagram
1
ENABLE
CHAN
DATA
SERIAL-TO-PARALLEL
LOOPBACK
FROM T
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(Table
HDLC
X
442) bits are set, the receive HDLC FIFO will
(continued)
CHAN
VALID
TYPE
DATA
TMXF28155/51 Super Mapper
8
Figure 64
INTERRUPTS
FIFOs/
below). This block
INTS.
5-9028(F)r.1
519