tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 491

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description
21.9.1 Signaling State Mode Source Selection
The signaling state mode source is selected by programming FRM_R_FGSRC in
Receive Signaling Link Register 33 (R/W) on page
gramming the state mode. If so, the host will have to program the state mode for all of the time slots on each of the
links. The default state mode selected is 16-state signaling.
It is possible for the state mode to be set by the values received on the CHI bus by the receive system interface. In
this mode, the signaling processor will constantly monitor those values and update the state mode for each of the
time slots on each link.
21.9.2 Signaling State Mode Selection
The signaling state mode for each time slot is selected by programming bits 5 and 6 of FRM_RSLR0—
FRM_RSLR31, Receive Signaling Link Registers 0—31 (R/W) in
nition for each of those 32 registers is shown below.
Table 577. Receive Signaling Link Registers 0—31 Bit Description
The signaling state mode definitions are shown in the table below.
Table 578. Receive Signaling Link Registers 0—31 G-Bit and F-Bit Description
The signaling state mode for DS1 type links should be set to match the function of each time slot. The signaling
state mode does not apply to CEPT type links and the value must be kept in the reset state which is 00. The signal-
ing state mode for CMI type links must be set to 11.
The 16-state mode, which is the state mode selected out of reset, can be used on SF type DS1 links in order to
detect a toggle code. In this case, signaling will be collected over two superframes and stored as a 4-bit code.
When programming the state mode for each time slot, the host can also program the D, C, B, and A bits in the
same register. Doing this will determine the default code forwarded to the transmit system or the transmit line inter-
face before the first valid signaling code has been extracted from the receive line or VT mapper interface.
Each of the links and time slots is completely independent from one another with respect to the signaling state
mode selection. Any combination is acceptable.
21.9.3 Signaling Source Selection
The signaling source is selected by programming FRM_R_SIGSRC in
ing Link Register 33 (R/W) on page
signaling processor will start extracting data from the receive line and store valid signaling codes into the D, C, B,
and A locations of FRM_RSLR0—FRM_RSLR31, Receive Signaling Link Registers 0—31 (R/W),
page 268
The receive signaling processor will automatically determine the link type and extract the correct signaling bit posi-
tions from each link. The receive signaling processor can simultaneously service any combination of CEPT, DS1,
and CMI type links. The receive signaling processor will extract robbed-bit signaling from DS1 links, common chan-
nel signaling from CEPT links, and time slot 0 signaling from CMI links compliant with the following standards.
Agere Systems Inc.
G and F
Bit 6
G
00
01
10
11
for each of the links.
Bit 5
F
269, bits [1:0]. If the source selected is the receive line interface, the receive
Bit 4
—
Signaling State Mode Selected
269, bit 2. The typical application will select the host for pro-
Bit 3
16 state (reset state)
D
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
no signaling
4 state
2 state
Table 372 on page 268
Table 374, FRM_RSLR33, Receive Signal-
Bit 2
C
(continued)
TMXF28155/51 Super Mapper
Table 374, FRM_RSLR33,
Bit 1
for each link. The bit defi-
B
Table 372 on
Bit 0
A
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