tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 541

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description
21.29 Superframer Register Addressing
Table 609 below summarizes the address map for the global and per link/channel registers of the superframer:
Table 609. Framer Addressing Map for the Global and Per Link/Channel Registers of the Superframer
21.29.1 Per Link Register Sections in Table 609
SIG = Signaling (see
PM = Performance Monitor (see
RDL = Receive (Facility) Data Link (see
TDL = Transmit (Facility) Data Link (see
SYS = System Interface (see
AR = Arbiter (Framer) (see
FF = Frame Formatter (Transmit Framer) (see
LC = Line Encoder/Decoders (see
HDLC = High-Level Data Link Control (see
RXP = High-Level Data Link Control (see
Agere Systems Inc.
15
0
the line encoder and TXP = 1 for the line decoder.
14
0
0
1
page
page
transmit HLDLC.
page
HDL9 HDL8 HDL7 HDL6 HDL5
LNK4 LNK3 LNK2 LNK1
HDLC Channels 1—64 (000000—111111)
288).
290).
13
0
304); RXP = 0 for the receive HDLC and TXP = 1 for the transmit HDLC.
Links 1—28 (00001—11100)
12
0
Section 12.9.1 Signaling Per Link Registers on page
11
Section 12.2 Arbiter (Framer) Global Registers on page
0
Section 12.13 System Interface, Arbiter, and Frame Formatter Mapping on page
Section 12.3 Performance Monitor Global Registers on page
10
0
Section 12.18 Line Encoder/Decoder Per Link Registers on page
Section 12.11 Receive Facility Data Link Configuration and Status Registers on
LNK0
Section 12.12 Transmit Facility Data Link Configuration and Status Registers on
Table 432 on page304
Address Pins (ADDR15—ADDR0)
9
0
Section 12.19 HDLC Per Channel Configuration and Status Registers on
Section 12.16 Frame Formatter Per Link Registers on page
RXP=0/
TXP=1
HDL4
Framer Global Registers
8
RXP=0/
TXP=1
7
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
) RXP = 0 for the receive HDLC and TXP = 1 for the
SIG6
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
Framer Functional Register Addresses
Others
267).
SIG5
PM5
5
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
0
(continued)
TMXF28155/51 Super Mapper
SIG4
PM4
245).
4
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
1
1
0
RDL3
TDL3
HDL3
SIG3
PM3
3
0
0
0
1
1
247).
Per Channel Register
Performance Monitor
Performance Monitor
Superframer Global
Transmit Data Link
Receive Data Link
(Transmit Framer)
System Interface
Frame Formatter
RDL2
SYS2
HDL2
TDL2
SIG2
PM2
AR (Framer)
2
0
1
0
1
303); RXP = 0 for
Reserved
Reserved
Signaling
HDLC
300).
RDL1
SYS1
HDL1
TDL1
SIG1
PM1
Res.
AR1
FF1
LC1
1
292).
RDL0
SYS0
HDL0
TDL0
SIG0
PM0
AR0
Res.
FF0
LC0
541
0