tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 256

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers
Table 342. FRM_HGR16, Receive HDLC Global Register 16 (R/W)
Table 343. FRM_HGR17, Receive HDLC Global Register 17 (R/W)
Table 344. FRM_HGR18, Receive HDLC Global Register 18 (R/W)
Table 345. FRM_HGR19, Receive HDLC Global Register 19 (R/W)
Table 346. FRM_HGR20, Receive HDLC Global Register 20 (R/W)
256
Address
Address
Address
Address
Address
0x80041
0x80042
0x80043
0x80044
0x80045
15:10
15:0
15:0
15:0
15:0
Bit
9:0
Bit
Bit
Bit
Bit
FRM_HRTHRSH1[9:0] Indicates the Threshold Levels for the Rx FIFOs.
FRM_RH_IS[15:0]
FRM_RH_IS[63:48]
FRM_RH_IS[31:16]
FRM_RH_IS[47:32]
Name
Name
Name
Name
Name
—
(continued)
Reserved. Must write to 0.
When a channel is enabled and its FIFO count incre-
ments to this value, its FRM_HRTHRSH status bit is
set. FRM_HRTHRSH0[9:0] or FRM_HRTHRSH1[9:0]
is selected on a per-channel basis with the
FRM_RTHRSEL
Receive HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 15—0 to bits 15:0.
Receive HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 63—48 to bits 15:0.
Receive HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 31—16 to bits 15:0.
Receive HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 47—32 to bits 15:0.
(Table
Function
Function
Function
Function
Function
442) parameter.
Agere Systems Inc.
May 2001
Default
Default
Default
Default
Default
Reset
Reset
0x000
Reset
Reset
Reset
0x00
0
0
0
0