tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 514

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
The host will indicate this state by resetting the Tx stack empty bit,
the new D bits will be transmitted; otherwise, the previous D bits will be retransmitted. If the Tx stack empty bit was
0 at the beginning of the SLC -96 superframe, then the bit will be set to 1, indicating a request for new D bits.
When enabled using the FRM_ASRC
has been reached. For SLC -96, both terminal (F
the insertion of D bits and the reporting of stack empty to the host.
Before enabling a link for the SLC -96 format or enabling this block for insertion, the host should initialize the stack
and set the Tx stack empty bit to 0. If not, the data link block will transmit the reset state of the stack, which is arbi-
trary.
21.22.10 DDS Transmit Data Link Stack
If enabled for insertion, this block will always source the DDS data link bits to any DDS Tx link. DDS superframes
are 12 frames with the data link bits located in bit number 6 of time slot 24 of every frame. Thirty-six frames of data
link bits are stored in the stack.
The DDS stack is stored in the shared Tx stack as follows.
Table 593. Shared Tx FDL Stack Format for DDS Frames
* The value held in the bits left blank should be ignored by the host.
Transmission of the DDS stack will take 4.5 ms to complete, during which time the host should refill the system
stack if the data link bits need to change.
Near the beginning of every third DDS superframe, the Tx data link block will determine whether a new set of data
link bits is available to be transmitted. The host will indicate this state by resetting the Tx stack empty bit. If this is
the case, the new data link bits will be transmitted; otherwise, the previous data link bits will be retransmitted. If the
Tx stack empty bit was 0 at the beginning of the set of superframes, then the bit will be set to 1, indicating a request
for new data link bits.
When enabled, using the FRM_ASRC bit, the Sa bits should only be inserted when the proper alignment has been
reached. For DDS links, only terminal frame (F
link bits and the reporting of stack empty to the host.
Before enabling a link for the DDS format or enabling this block for insertion, the host should initialize the stack and
set the Tx stack empty bit to 0. If not, the data link block will transmit the reset state of the stack, which is arbitrary .
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Provides three superframes of data link bit storage for transmission on DDS links.
Provides interrupt for stack empty.
Performs retransmission of stack when update has yet to be performed.
Provides host access to stack using processor clock to provide fast access.
Word
0*
1*
2
3
4
D1
D1
D1
15
—
—
D2
D2
D2
14
—
—
D3
D3
D3
13
—
—
D4
D4
D4
12
—
—
(Table
D5
D5
D5
11
—
—
412) bit, the D bits should only be inserted when the proper alignment
D6
D6
D6
10
—
—
T
) is required for insertion. This condition affects the insertion of data
T
) and signaling (F
D7
D7
D7
—
—
9
D8
D8
D8
—
—
8
D9
D9
D9
—
—
7
S
FRM_TXSE_IS
) frames need to be valid. This condition effects
D10
D10
D10
—
—
6
(continued)
D11
D11
D11
—
—
5
(Table
D12
D12
D12
—
—
4
414). If this is the case,
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Agere Systems Inc.
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May 2001
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