tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 524

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
Parallel Bus System Interface Mode. This interface consists of a 17-bit wide parallel bus operating at
19.44 Mbits/s, 9 bits of which form a byte of data and a data parity bit while the other 8 bits contain the signaling
and control information. A clock and frame sync are expected in both the receive and transmit directions. For a
28-link device, only 1/3 of the bytes are populated. In the transmit direction the unpopulated bytes are 3-stated,
while in the receive direction they are ignored. Three 28-link devices (Super Mappers) can be connected in parallel
to the telecom bus for implementing an STS-3 (STM-1) rate interface.
Note: The Tx system is defined as the interface that sends data out of the chip and toward the system (non-
21.26.2 System Interface References/Standards
21.26.3 Transmit/Receive System Interface Features
The features supported in the system interface are summarized below:
21.26.4 Double NOTFAS System Time-Slot (FRM_DNOTFAS
This mode is applicable to the CHI and parallel bus system interface modes. In the default case
(FRM_DNOTFAS = 0
interface and expected by the receive system interface.
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ITU G.783 characteristics of synchronous digital hierarchy (SDH) equipment functional blocks.
ITU Q.511 exchange interfaces towards other exchanges.
Data rates of 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, and 19.44 Mbyte/s.
Clock rates of 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz, and 19.44 MHz.
A global input clock and frame sync (CHI and parallel bus system interface modes).
Byte offset—2.048 Mbits/s, 0—31 bytes.
Byte offset—4.096 Mbits/s, 0—63 bytes.
Byte offset—8.192 Mbits/s, 0—127 bytes.
Bit offset (CHI mode).
1/2-bit offset (CHI mode).
1/4-bit offset (CHI CMS mode).
Clock mode select (CMS) (CHI mode).
Associated signaling mode (ASM) (CHI mode).
Double time slot mode, CHIDTS (CHI mode).
Double NOTFAS system time slot, FRM_DNOTFAS
Sampled clock edge for transmit system frame sync (CHI mode).
Global programmable stuffed time slot position in DS1 mode (CHI mode).
Global programmable stuffed byte in DS1 mode (CHI and parallel bus system interface modes).
Global single time slot loopback address for system or line.
Programmable automatic system AIS (loss of frame alignment).
Programmable automatic system AIS (CEPT CRC-4 multiframe alignment timer expiration).
On-demand transmission of system AIS.
Programmable even/odd parity generation (parallel bus system interface mode).
SONET) interface. The Rx system receives data from the system. These designations are opposite of the
path definitions for the Super Mapper.
(Table
347)), both the FAS and NOTFAS time slots are transmitted by the transmit system
(Table
347) (CHI and parallel bus system interface modes).
(Table
347)) Mode
(continued)
Agere Systems Inc.
May 2001