tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 116

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers
Table 118. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) (continued)
Table 119. TMUX_TFRAMEOFFSET, Transmit High-Speed Offset Control Parameters (R/W)
)
Table 120. TMUX_SD_CTL[1—6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W)
116
Address
0x4004B
Address
0x4004D
Address
0x4004E
0x4004F
0x4004F
0x40050
0x40051
0x40052
15:0
14:7
15:0
15:0
15:13
12:11
2:0
6:3
2:0
10:4
Bit
Bit
Bit
3:0
2
1
0
TMUX_SDNSCLEAR[18:3]
TMUX_SDNSCLEAR[2:0]
TMUX_TPOAC_OEPMON Transmit TOAC Odd or Even Parity Monitor. Control
TMUX_SDNSSET[18:3]
TMUX_SDNSSET[2:0]
TMUX_TLROWCNT[3:0]
TMUX_SDBSET[15:0]
TMUX_TLCOLCNT[6:0]
TMUX_TLSTSCNT[1:0]
TMUX_SDMSET[7:0]
TMUX_SDLSET[3:0]
TMUX_TLBITCNT[2:0]
TMUX_TPOAC_C2
TMUX_TPOAC_J1
(continued)
Name
Name
Name
Signal Degrade Ns Set. Number of frames in a
monitoring block for signal degrade (SD).
Signal Degrade M Set. Threshold of the number of bad
monitoring blocks in an observation interval. If the
number of bad blocks is above this threshold, then SD is
set.
Signal Degrade L Set. Error threshold for determining
if a monitoring block is bad.
Signal Degrade B Set. Number of monitoring blocks.
Signal Degrade Ns Clear. Number of frames in a
monitoring block for SD.
Transmit Load Bit Count. Allows the output
STS-3/STM-1 (AU-4) frame to have any relationship to
the input frame sync pulse (THSSJ0J1V1I).
Transmit Load STS-1 Count. Same as above.
Transmit Load Column Count. Same as above.
Transmit Load Row Count. Same as above.
Transmit POAC C2 Byte Control. When 1, causes
the incoming POAC C2 value to be inserted into the C2
byte of the selected TPOAC STS-1 if the correspond-
ing TMUX_THSC2INS
serted. If the C2 is not inserted from register control or
from the transmit POAC channel, then its value
depends on SMPR_OH_DEFLT.
Transmit POAC J1 Byte Control. Control bit, when
set to a logic 1, causes the incoming POAC J1 value to
be inserted into the J1 byte of the selected TPOAC
STS-1 if the corresponding TMUX_THSJ1INS
(Table
inserted from register control or from the transmit
POAC channel, then its value depends on
SMPR_OH_DEFLT.
bit, when set to a logic 1, forces the input TOAC parity
checker to check for odd parity; otherwise, even parity
is checked on the transmit TOAC channel.
108) control bit is desasserted. If the J1 is not
Function
Function
Function
(Table
108) control bit is desas-
Agere Systems Inc.
May 2001
0000000
0x00000
0x00000
Default
Default
Default
0x0000
Reset
Reset
Reset
0000
0x00
000
0x0
00
0
0
0