tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 509

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description
21.22.2 Receive Data Link Functional Description
This block extracts facility data links bits and stores them in a microprocessor access register bank:
The respective bits will always be extracted from the framed aligned receive line payload and stored in the facility
data link stack regardless of other configuration bits. The processor will have control of being alerted to stack
updates through the interrupt mask registers.
All frame types:
21.22.3 SLC -96 Superframe Receive Data Link
Both basic frame alignment and multiframe alignment must be established before the data can be assumed valid.
The SLC -96 Fs bits are stored in the Rx stack as follows.
Table 589. Shared Rx Stack Format for SLC -96 Frames
* The value held in the bits left blank should be ignored by the host.
When the entire stack has been filled, the host is notified using the Rx stack ready interrupt. After the Rx stack
ready interrupt bit is set, the host has approximately 9 ms to read the stack.
21.22.4 DDS Receive Data Link Stack
DDS frames are numbered 1 through 12 with the data link bits located in bit 6 of time slot 24 in every frame. Only
basic frame alignment must be established for the data link bits to be extracted.
The DDS stack is stored in the shared Rx stack as follows.
Agere Systems Inc.
D bits from the SLC -96 multisuperframe.
Sa bits from time slot 0 in CEPT basic and CRC-4 multiframes.
Data link bits from DDS frames.
Support clear-on-read status and interrupt bits based on the setting of the input select signal.
Delineates the SLC -96 data link in the Fs signaling frame, extracts the 24 D bits, and stores in the internal mem-
ory stack.
Provides interrupt for stack ready.
Provides host access to stack using processor clock.
Supports loss of frame status.
Extracts data link bit (bit 6) from time slot 24 and stores into stack.
Provides interrupt for stack ready.
Provides host access to stack using processor clock to provide fast access.
Supports loss of frame status.
Word
1*
2*
3*
4*
0
SB2
C1
15
0
0
0
SB3
C2
14
0
0
0
M1
C3
13
0
0
0
M2
C4
12
1
0
0
C5
M3
11
1
0
0
C6
A1
10
1
0
0
C7
A2
9
0
0
0
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
C8
S1
8
0
0
0
C9
S2
7
0
0
0
C10 C11 SB1
S3
6
1
0
0
(continued)
TMXF28155/51 Super Mapper
S4
5
1
0
0
SB4
4
1
0
0
3
0
0
0
0
0
2
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
509