tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 577

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
24 Test-Pattern Generation/Detection Functional Description
24.5.2 TPG Clock Source
The Super Mapper TPG uses four source clocks provided by the cross connect as input at the appropriate rate to
generate the test patterns. These are shown in
being supplied by the XC block, except the DS3 clock (which is provided via the XC3 crosspoint by the M13 or SPE
block).
24.5.3 TPG Transmit Edge Select
The edge of the clock TPG_CLKx that is used to source the data is provisionable to either the rising edge
TPG_EDGEx = 1
tern sources.
24.5.4 TPG Test-Pattern Framing
The test pattern can be transmitted either unframed or as the payload of a framed signal as defined in ITU-T Rec-
ommendation O.150. The DS1 continuous-idle signal is always framed. The test-pattern framing is determined by
the TPG_FRAMEx register values
a test-pattern embedded in a framed signal. Additionally, a TPG_ESF bit
frame operation is enabled (DS1 only).
Table 624. TPG Framing Controls (TPG_FRAMEx = 1)
The DS1 idle data signal is always superframe (SF) framed. The associated SYNC signal is generated but may
safely be ignored if not used.
24.5.5 DS1 TPG Framing
For DS1 signals, the frame bit in the 12th frame of each superframe is inverted if TPG_FINV0 = 1 (
Table
For ESF modes, the transmitted data-link pattern is a continuous repeat of the contents of the TPG_ESFDL[15:0]
(Table
injected via TPG_CRC6EINSx register bits
TPG_CRC6EINSx bit transitions from 0 to 1.
24.5.6 E1 TPG Framing
For E1 signals, the frame alignment signal (normally 0011011) is transmitted with the last bit inverted (0011010) if
TPG_FINV = 1
Each transmitted E1 multiframe contains a CRC-4 cyclic redundancy check mechanism per Recommendation
G.704 Section 2.3. CRC-4 errors may be injected via TPG_CRC4EINSx register bits
error event is generated each time that the TPG_CRC4EINSx bit transitions from 0 to 1.
Agere Systems Inc.
Index
(x)
508).
0
1
2
4
5
504). Each ESF superframe is also checked for CRC-6 errors per ANSI T1.403. These CRC errors may be
(Table 507
Data Rate
(Tables
DS1
DS2
DS3
E1
—
507, 508, 509, and 510) or the falling edge TPG_EDGEx = 0 for each of the five test-pat-
and
Table
Transparent mode (test sequence bits
(Table 507
508).
in signaling bit positions)
(Table
SF (TPG_ESF = 0)
Continuous idle
and
Figure 100, TPG Block Interface Block Diagram on page 576
DS3—gated PRBS sequence (framing via M13)
503). A single CRC-6 error event is generated each time that the
Table
E1 with common channel signaling, CRC-4
508): 0 represents an unframed signal, while 1 represents
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Unframed PRBS sequence
Framing
(Table
User-settable data-link pattern CRC-6
TMXF28155/51 Super Mapper
507) determines if extended super-
ESF (TPG_ESF = 1)
(continued)
(Table
generate/check
503). A single CRC-4
NA
Table 507
as
and
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