tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 532

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
Figure 74. CHI TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS = 1 (CEX = 3 and CER = 6,
The timing figures shown are functional timing diagrams. See
page 46
ifications.
21.26.16 The Parallel Bus System Interface Mode
This interface consists of a 16-bit wide parallel bus operating at 19.44 Mbyte/s, nine bits of which form a byte of
data and a data parity bit while the other eight bits contain the signaling and control information (A, B, C, and D sig-
naling bits, F and G signaling state bits, P parity bit, and a don’t care bit). A clock and frame sync are expected in
both the receive and transmit directions.
system interface mode. The timing specifications for this interface are in the
ing on page 47
is fixed in this mode.
532
RCHIDATA
TCHIDATA
TCHICK/
RCHICK
TCHIFS/
RCHIFS
in the Timing Characteristics section of this data sheet for CHI interface and clock timing parameter spec-
Respectively)
Figure 75. Parallel Bus System Interface Mode of the Transmit System Interfac e
in the Timing Characteristics section of this data sheet. The offset between the frame sync and data
ALIGNER
FORMATTER
FRAME
FRAME
HIGH IMPEDANCE
28
TDM
28
1
CHI FRAME SYNC IS SAMPLED ON THE FALLING EDGE
Figure
2
CEX = 3
75, below, shows the transmit system interface in the parallel bus
28
TDM
3
FANOUT
4
BIT 0, TS 0
TRANSMIT SYSTEM
BUFFER
5
Section 5.5 Concentration Highway (CHI) Timing on
CER = 6
1
SLIP
TCLK
RECEIVE SYSTEM
TFS
ADAPTATION
6
BUFFER
BIT 0, TS 0
RATE
(continued)
PLL
7
Section 5.6 Parallel System Bus Tim-
8
28
RS_D[16:1]
RS_GFS
RS_GCLK
RS_GTCLK
TS_GFS
TS_GCLK
TS_D[16:1]
BIT 1, TS 0
BIT 1, TS 0
Agere Systems Inc.
May 2001
5-8984(F)
5-9037(F)