tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 293

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers
Table 417. System Interface, Arbiter, and Frame Formatter Link Register Address Indexing
Read: for link 1 on the receive path, the hexidecimal digit L is 0x0 and the hexidecimal digit P is 0x2.
12.14 System Interface Per Link Registers
Table 418. FRM_SYSLR1, System Interface Link Register 1 (R/W)
* See
Agere Systems Inc.
Address*
0x8LPE0
Link
—
—
1
2
3
4
5
6
7
1
2
3
4
5
6
7
Table 417
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
—
for values of L and P .
L
14:8
Bit
6:4
3:2
15
7
1
0
FRM_BYOFF[6:0] CHI Byte Offset. This bit is only applicable in the CHI mode. 0000000
0xA
0xC
0xE
0xB
0xD
FRM_QUAROFF Quarter Bit Offset. When set to 1, an offset of 1/4 bit is
0x2
0x4
0x6
0x8
0x3
0x5
0x7
0x9
0xF
FRM_HALFOFF
—
—
FRM_OFF[2:0]
P
Name
—
—
—
Link
10
11
12
13
14
15
10
11
12
13
14
15
8
9
8
9
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
Reserved. Must write to 0.
Reserved. Must write to 0.
CHI Bit Offset.
Reserved. Must write to 0.
Half Bit Offset. When set to 1, an offset of 1/2 bit is added to
offsets.
added to the offsets. CHI CMS mode only.
L
Transmit Path (P is odd))
Receive Path (P is even)
(continued)
0xA
0xC
0xE
0xB
0xD
0x0
0x2
0x4
0x6
0x8
0x1
0x3
0x5
0x7
0x9
0xF
P
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Link
16
17
18
19
20
21
22
23
16
17
18
19
20
21
22
23
Function
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
L
TMXF28155/51 Super Mapper
0xC
0xD
0x0
0x2
0x4
0x6
0x8
0xA
0xE
0x1
0x3
0x5
0x7
0x9
0xB
0xF
P
Link
24
25
26
27
28
24
25
26
27
28
—
—
—
—
—
—
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
0x3
—
—
—
—
—
—
L
Default
Reset
000
0x0
0x2
0x4
0x6
0x8
0x1
0x3
0x5
0x7
0x9
0
0
0
0
0
—
—
—
—
—
—
P
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