tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 380

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description
Table 525. STS-1 P-REI Interpretation
The TMUX allows access to the G1-REI errored bit count for each STS-1/STM-1 in TMUX_G1ECNT[1—3][15:0]
(Table 128 on page
counter(s) will count in bit or block mode, depending on the value of TMUX_BITBLKG1
Upon the configured performance monitor (PM) interval, the value of the internal running counter is placed into the
holding registers TMUX_G1ECNT[1—3][15:0] and then cleared. Depending on the value of
SMPR_SAT_ROLLOVER
either roll over or stay at its maximum value until cleared.
Path User Byte F2 Monitor. The TMUX monitors the path user channel in the F2 byte of each STS-1/STM-1. The
F2 byte(s) will be stored in TMUX_F2MON0[1—3][7:0]
updated after a number of consecutive frames of identical F2[7:0] as determined by the value in
TMUX_CNTDF2[3:0]
of frames prior to updating the F2 register. Any change to F2 monitor registers will be reported in
TMUX_RF2MOND[1—3]
TMUX also maintains a history of the previous valid F2 byte in TMUX_F2MON1[1—3][7:0]
uous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame state.
H4 Multiframe Indicator. The H4 byte is allocated for use as a mapping specific indicator byte. For VT-structured
SPEs, this byte is used as a multiframe indicator.
The TMUX passes the H4 byte of each STS-1 onto the low-speed telecom bus so that it can be monitored by the
VT mapper block. The TMUX also indicates when the H4 byte(s) has a value of 0x01 by asserting the RLSV1 out-
put pin (pin number W4) on the telecom bus during that frame.
Note: The three H4 bytes of an STS-3 signal can occur at any time with respect to one another within a frame.
Path User Byte F3 Monitor. The TMUX monitors the second path user channel in the F3 byte for each
STS-1/STM-1. The F3 byte(s) for each STS-1/STM-1 is stored in TMUX_F3MON0[1—3][7:0]
page
on pag
tern must be identical for the programmed number of frames prior to updating the F3 register.
380
101). Each register will be updated after a number determined by the value in TMUX_CNTDF3[3:0]
e99) of consecutive frames of identical F3[7:0] monitor bytes on that particular STS-1. That is, the 8-bit pat-
G1[7:4] Code
120), which is the accumulated error count from G1[3:0] byte of the STS-1/STM-1 signal. The
(Table 99 on page
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1111
. . .
(Table
(Table 67 on pag
83), with interrupt mask bits, TMUX_RF2MONM[1—3]
99). That is, the 8-bit pattern must be identical for the programmed number
e68) in the microprocessor interface block, the internal counter will
(continued)
(Table 104, starting on page
Code Interpretation
0 (no errors)
0 (no errors)
0 (no errors)
. . .
1
2
3
4
5
6
7
8
101). Each register will be
(Table 87 on page89
(Table 95 on page95
(Table
(Table 104 on
Agere Systems Inc.
104). The contin-
May 2001
(Table 99
). The
).