PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 101

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
After ‘RESET’ all control registers except the XFIFO and XS1-16 are initialized to defined
values.
Unused bits have to be set to logical ‘0’.
The status registers are only readable and are updated by the QuadFALC.
Transmit FIFO (WRITE) XFIFO
XFIFO
Command Register (Write)
Value after RESET: 00
CMDR
RMC…
RRES…
XREP…
7
7
RMC
XF7
Up to 32 bytes/16 words of received data can be read from the RFIFO
following a RPF or a RME interrupt.
Writing data to XFIFO can be done in 8-bit (byte) or 16-bit (word)
access. The LSB is transmitted first.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO
following a XPR (or ALLS) interrupt.
Receive Message Complete
Confirmation from CPU to QuadFALC that the current frame or data
block has been fetched following a RPF or RME interrupt, thus the
occupied space in the RFIFO can be released.
Receiver Reset
The receive line interface except the clock and data recovery unit
(DPLL), the receive framer, the one second timer and the receive
signaling controller are reset. However the contents of the control
registers will not be deleted.
Transmission Repeat
If XREP is set to one together with XTF (write 24
QuadFALC repeatedly transmits the contents of the XFIFO (1 … 32
bytes) without HDLC framing fully transparently, i.e. without
FLAG,CRC.
The cyclic transmission is stopped with a SRES command or by
resetting XREP.
RRES
H
XREP
XRES
101
XHF
XTF
Operational Description E1
XME
0
0
H
SRES
to CMDR), the
XF0
PEB 22554
(x00/x01)
(x02)
09.98