PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 345

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

shorter than 1.5 ms (F4, F12, F72) or 3 ms (ESF). Otherwise, reactions of initiated
simulations may occur at later steps.
Framing Error Counter (READ)
FECL
FECH
FE15…FE0…
Semiconductor Group
7
7
FE15
FE7
Framing Errors
This 16-bit counter will be incremented when incorrect FT and FS bits
in F4, F12 and F72 format or incorrect FAS bits in ESF format are
received.
Framing errors will not be counted during asynchronous state. The
error counter will not roll over.
During alarm simulation, the counter will be incremented twice.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DFEC has
to be set. With the rising edge of this bit updating the buffer will be
stopped and the error counter will be reset. Bit DEC.DFEC will
automatically be reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter will be latched and then automatically reset. The latched error
counter state should be read within the next second.
345
Operational Description T1 / J1
0
0
FE0
FE8
PEB 22554
(x50)
(x51)
09.98