PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 240

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Transmit Direction
FS/DL data on system transmit highway (XDI), time-slot 0.
Figure 61
Transmit FS/DL Bits on XDI
Transmit Signaling Controller
Similar to the receive signaling controller the same signaling methods and the same
time-slot assignment are provided. The QuadFALC will perform the following signaling
and data link methods:
• HDLC or LAPD access
• CAS Bit Robbing
Semiconductor Group
The transmit signaling controller of the QuadFALC performs the FLAG generation,
CRC generation, zero bit-stuffing and programmable IDLE code generation. Buffering
of transmit data is done in the 64 byte deep XFIFO. The signaling information will be
internally multiplexed with the data applied to port XDI or XSIG.
In signaling controller transparent mode, fully transparent data transmission without
HDLC framing is performed. Optionally the QuadFALC supports the continuous
transmission of the XFIFO contents.
Operating in HDLC or BOM mode “flags” or “idle” may be transmitted as interframe
timefill. The QuadFALC offers the flexibility to insert data during certain time-slots. Any
combinations of time-slots may be programmed separately for the receive and
transmit directions.
The signaling controller inserts the bit stream either on the transmit line side or if
external signaling is enabled on the transmit system side. Signaling data may be
sourced internally from registers XS1-12 or externally at port XSIG, which is selected
by register PC1-4.
In external signaling mode the signaling data is sampled with the working clock of the
transmit system interface (SCLKX) in conjunction with the transmit synchronous pulse
(SYPX). Data on XSIG will be latched in the bit positions 5-8 per time-slot, bits 1-4 will
MSB
1
2
3
FS/DL Time-Slot
4
240
5
6
Functional Description T1 / J1
7
FS/DL
LSB
8
FS/DL Data Bit
ITD06460
PEB 22554
09.98