PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 33

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Interrupt Interface
Special events in the QuadFALC are indicated by means of a single interrupt output with
programmable characteristics (open drain, push-pull; IPC register), which requests the
CPU to read status information from the QuadFALC, or to transfer data from/to
QuadFALC.
Since only one INT request output is provided, the cause of an interrupt must be
determined by the CPU by reading the QuadFALC’s interrupt status registers (CIS, GIS,
ISR0-4) that means the interrupt on pin INT and the interrupt status bits are reset by
reading the interrupt status registers. Register ISR0-4 are from type “Clear on Read“.
The structure of the interrupt status registers is shown in figure 8.
Figure 8
QuadFALC Interrupt Status Register Structure
Each interrupt indication of registers ISR0-4 can be selectively masked by setting the
corresponding bit in the corresponding mask registers IMR0-4. If the interrupt status bits
are masked, they neither generate an interrupt at INT nor are they visible in ISR0-4.
CIS, the non-maskable Channel Interrupt Status Register, serves as a pointer to pending
channel related global interrupt status registers. After the QuadFALC has requested an
interrupt by activating its INT pin, the CPU should first read the Channel Interrupt Status
Semiconductor Group
Global Interrupt Status
(Per Channel)
GIS
IMR4
ISR4
IMR3
IMR2
ISR3
ISR2
Channel Interrupt Status
CIS
ISR4
ISR3 ISR2
33
ISR1
ISR0
ISR0
ISR1
IMR0
IMR1
Functional Description E1
C4
C3
PEB 22554
C2
ITS10309
C1
09.98