PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 325

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

IRSP …
IRSC …
IXSP …
IXSC …
Semiconductor Group
1…
Internal Receive System Frame Sync Pulse
0…
1…
Internal Receive System Clock
Only applicable if bit GPC1.SMM is cleared. If GPC1.SMM is set
SCLKR1 of channel 1 provides the working clock for all four channels.
0…
1…
Internal Transmit System Frame Sync Pulse
0…
1…
Internal Transmit System Clock
The center function of the DCO-R circuitry is disabled. The
The frame sync pulse for the receive system interface is
The frame sync pulse for the receive system interface is
The working clock for the receive system interface is sourced by
The working clock for the receive system interface is sourced
The frame sync pulse for the transmit system interface is
The frame sync pulse for the transmit system interface is
clock on pin SYNC or
- a gapped clock is provided at pin RCLKI and this clock is
inactive or stopped.
generated clock (DCO-R) is frequency frozen in that moment
when no clock is available at pin SYNC or pin RCLKI. The
DCO-R circuitry will starts synchronization as soon as a clock at
pins SYNC or RCLKI appears.
sourced by SYPR.
internally sourced by the DCO-R circuitry of each channel. This
internally generated frame sync could be output active low on
pin RP(A-D). RPC(2-0) = 001. Programming the receive
time-slot offset is also done in the same way as it is done for the
external SYPR. For correct operation bit IRSC must be set.
SYPR is ignored.
SCLKR of each channel or in receive elastic buffer bypass
mode from the corresponding extracted receive clock RCLK.
internally by DCO-R or in bypass mode by the extracted receive
clock of each channel. SCLKR is ignored.
sourced by SYPX.
internally sourced by the DCO-R circuitry of each channel.
Additionally, the external XMFS signal defines the transmit
multiframe begin. XMFS is enabled or disabled via the
multifunction ports. For correct operation bits CMR2.IXSC /
IRSC must be set. SYPX is ignored.
325
Operational Description T1 / J1
PEB 22554
09.98