PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 349

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Bit Error Counter (READ)
BECL
BECH
BEC15…BEC0… Bit Error Counter
Semiconductor Group
7
7
BEC15
BEC7
If the PRBS monitor is enabled by LCR1.EPRM= 1 this 16-bit counter
will be incremented with every received PRBS bit error in the PRBS
synchronous state FRS1.LLBAD=1. The error counter will not roll
over.
During alarm simulation, the counter will be incremented continuously
with every second received bit.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the PRBS bit error counter bit
DEC.DBEC has to be set. With the rising edge of this bit updating the
buffer will be stopped and the error counter will be reset. Bit
DEC.DBEC will automatically be reset with reading the error counter
high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter will be latched and then automatically reset. The latched error
counter state should be read within the next second.
349
Operational Description T1 / J1
0
0
BEC0
BEC8
PEB 22554
(x58)
(x59)
09.98