PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 174

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

RMB…
CASC…
CRC4…
SA6SC…
RPF…
Interrupt Status Register 1 (Read)
ISR1
All bits are reset when ISR1 is read.
If bit GCR.VIS is set to ‘1’, interrupt statuses in ISR1 may be flagged although they are
masked via register IMR1. However, these masked interrupt statuses neither generate a
signal on INT, nor are visible in register GIS.
LLBSC…
Semiconductor Group
7
LLBSC
Line Loop Back Status Change
Receive Multiframe Begin
This bit is set with the beginning of a received CRC multiframe related
to the internal receive line timing.
In CRC multiframe format FMR2.RFS1 = 1 or in doubleframe format
FMR2.RFS1/0 = 01 this interrupt occurs every 2 msec. If
FMR2.RFS1/0 = 00
doubleframe (512 bits).
Received CAS Information Changed
This bit is set with the updating of a received CAS multiframe
information in the registers RS1-16. If the last received CAS
information changed from the previous received updating is started.
This interrupt will only occur in the TS0 and TS16 synchronous state.
The registers RS1-16 should be read within the next 2 ms otherwise
the contents may be lost.
Receive CRC4 Error
Receive SA6-Bit Status Changed
With every change of state of the received SA6-bit combinations this
interrupt will be set.
Receive Pool Full
32 bytes of a frame have arrived in the receive FIFO. The frame is not
yet completely received.
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
0...
1...
RDO
No CRC4 error occurs.
The CRC4 check of the last received submultiframe failed.
ALLS
XDU
this
174
XMB
interrupt
will
Operational Description E1
XLSC
be
generated
0
XPR
PEB 22554
(x69)
every
09.98