PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 47

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Receive Signaling Controller
Each of the four signaling controller can be programmed to operate in various signaling
modes. The QuadFALC will perform the following signaling and data link methods:
• HDLC or LAPD access
• S
• Channel Associated Signaling CAS
Semiconductor Group
In case of common channel signaling the signaling procedure HDLC/SDLC or LAPD
according to Q.921 will be supported. The signaling controller of the QuadFALC
performs the FLAG detection , CRC checking, address comparisson and zero
bit-removing. The received data flow and the address recognition features can be
performed in very flexible way, to satisfy almost any practical requirements.
Depending on the selected address mode, the QuadFALC performs a 1 or 2 byte
address recognition. If a 2-byte address field is selected, the high address byte is
compared with the fixed value FEH or FCH (group address) as well as with two
individually programmable values in RAH1 and RAH2 registers. According to the
ISDN LAPD protocol, bit 1 of the high byte address will be interpreted as
COMMAND/RESPONSE bit (C/R) and will be excluded from the address comparison.
Buffering of receive data is done in a 64 byte deep RFIFO. Refer also to chapter 4.1.
In signaling controller transparent mode, fully transparent data reception without
HDLC framing is performed, i.e. without FLAG recognition, CRC checking or
bit-stuffing. This allows user specific protocol variations.
The QuadFALC offers the flexibility to extract data during certain time-slots. Any
combination of time-slots may be programmed independently for the receive and
transmit direction.
The QuadFALC supports the S
follows:
- the access via registers RSW
- the access via registers RSA4-8, capable of storing the information for a complete
multiframe
- the access via the 64 byte deep receive FIFO of the signaling controller. This S
access gives the opportunity to receive a transparent bit stream as well as HDLC
frames where the signaling controller automatically processes the HDLC protocol.
Any combination of S
selected by XC0.SA8-4. The access to the RFIFO is supported by ISR0.RME / RPF.
The signaling information is carried in time-slot 16 (TS16). Receive data is stored in
registers RS1-16 on the CAS multiframe boundary. The signaling controller samples
the bit stream either on the receive line side or if external signaling is enabled on the
receive system side. External signaling is enabled by selecting the RSIG pinfunction
via register PC1-4.
Optionally the complete CAS multiframe may be transmitted on pin RSIG. The
signaling data is clocked out with the working clock of the receive highway (SCLKR)
in conjunction with the rec. synchron. pulse (SYPR). Data on RSIG will be transmitted
a
bit Access
a
bits which should be extracted and stored in the RFIFO may be
a
bit signaling of time-slot 0 of every other frame as
47
Functional Description E1
PEB 22554
09.98
a
bit