PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 320

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

XBS1...0…
System Interface Control 2 (Read/Write)
Value after RESET: 00
SIC2
FFS …
SSF …
CRB …
SSC2 …
Semiconductor Group
7
FFS
Transmit Buffer Size
00… By-pass of transmit elastic store
01… buffer size : 1 frame
10… buffer size : 2 frames
11… buffer size : 96 bits
Force Freeze Signaling
Setting this bit disables updating of the receive signaling buffer and
current signaling information is frozen. After resetting this bit and
receiving a complete superframe updating of the signaling buffer is
started again. The freeze signaling status could be also automatically
generated by detecting the Loss of Signal alarm or a Loss of Frame
Alignment or a receive slip (only if external register access via RSIG
is enabled). This automatic freeze signaling function is logically ored
with this bit.
The current internal freeze signaling status is output on pin RP(A-D)
/ pin function FREEZ which is selected by PC(1-4).RPC(2-0) = 110.
Additionally this status is also available in register SIS.SFS.
Serial Signaling Format
Only applicable if pin function R/XSIG is selected.
0…
1…
Center Receive Elastic Buffer
Only applicable if the time-slot assigner is disabled ( PC1-4.RPC2-0
= 001 ) , no external or internal synchronous pulse receive is
generated.
A transition from low to high will force a receive slip and the read-
pointer of the receive elastic buffer is centered. The delay through the
buffer is set to one half of the current buffer size. It should be hold high
for at least two 1.544 MHz periods before it is cleared.
Select System Clock
SSF
H
Bits 1-4 in all time-slots except time-slot 0 are cleared.
Bits 1-4 in all time-slots except time-slot 0 are set high.
CRB
SSC2
320
SICS2
Operational Description T1 / J1
SICS1
SICS0
0
PEB 22554
(x3F)
09.98