PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 165

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

CRC Error Counter 2 (Read)
CEC2L
CEC2H
CC15…CC0…
Semiconductor Group
7
7
CC15
CC7
CRC Error Counter (Reported from TE via Sa6 -Bit)
Depending of bit LCR1.EPRM the error counter increment is selected:
LCR1.EPRM=0:
If doubleframe format is selected, CEC2H/L has no function. If CRC-
multiframe mode is enabled, CEC2H/L works as SA6 Bit error
indication counter (16 bits) which counts the SA6 Bit sequence 0001
and 0011in every received CRC submultiframe.
Incrementing the counter is only possible in the multiframe
synchronous state FRS0.LMFA = 0.
SA6 Bit sequence: SA61, SA62, SA63, SA64 = 0001 or 0011 where
SA61 is received in frame 1 or 9 in every multiframe.
Pseudo Random Bit Sequence Error Counter
LCR1.EPRM=1:
This 16-bit counter will be incremented with every received PRBS bit
error in the PRBS synchronous state FRS1.LLBAD = 1. The error
counter will not roll over.
During alarm simulation, the counter is incremented once per
submultiframe up to its saturation.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC2
has to be set. With the rising edge of this bit updating the buffer will
be stopped and the error counter will be reset. Bit DEC.DCEC2 will
automatically be reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter will be latched and then automatically reset. The latched error
counter state should be read within the next second.
165
Operational Description E1
0
0
CC0
CC8
PEB 22554
(x58)
(x59)
09.98