PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 30

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PEB22554

Manufacturer Part Number
PEB22554
Description
ICs for Communications
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

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Table 2
Data Bus Access (16-Bit Motorola Mode)
BLE
0
0
1
1
Table 3
Selectable Bus and Microprocessor Interface Configuration
ALE
GND/VDD
GND/VDD
switching
The assignment of registers with even/odd addresses to the data lines in case of 16-bit
register access depends on the selected microprocessor interface mode:
Siemens/Intel
Motorola
Data Lines
n: even address
Complete information concerning register functions is provided in – Detailed Register
Description.
FIFO Structure
In transmit and receive direction of the signaling controller 64-byte deep FIFOs for each
channel are provided for the intermediate storage of data between the system internal
highway and the CPU interface. The FIFOs are divided into two halves of 32-bytes. Only
one half is accessible to the CPU at any time.
Semiconductor Group
A0
0
1
0
1
IM
1
0
0
D15
Register Access
FIFO word access
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
Motorola
Intel
Microprocessor interface
Intel
(Adr. n + 1)
(Adr. n)
30
D8
D7
(Adr. n)
(Adr. n + 1)
Functional Description E1
D0 – D7
D8 – D15
None
QuadFALC Data Pins
Used
D0 – D15
Bus Structure
demultiplexed
demultiplexed
multiplexed
PEB 22554
D0
09.98

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