PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 321

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

SICS2 …0
Semiconductor Group
Setting this bit together with SIC1.SSC1/0 enables the system
interface running with a clock of 1.544 , 3.088, 6.176 or 12.352 MHz.
Refer also to register SIC1.SSC1/0.
System Interface Channel Select
Only applicable if the system clock rate is greater than 1.544 /
2.048MHz .
Received data is transmitted on pin RDO / RSIG or received on XDI
/ XSIG with the selected system data rate. If the data rate is greater
than 1.544 / 2.048 MBit/s the data is output or sampled in half , a
quarter or a 1/8 of the 125 µsec. They will not be repeated. The time
where the data is active during a 488 / 648 nsec time-slot is called in
the following a channel phase. RDO / RSIG are cleared while XDI /
XSIG are ignored for the remaining time of the 488 / 648 nsec or for
the remaining channel phases. The channel phases are selectable
with these bits.
000 …data active in channel phase 1, valid if system data rate is 16 /
001 …data active in channel phase 2, valid if data rate is 16 / 8 / 4 or
010 …data active in channel phase 3, valid if data rate is 16 / 8 or 12
011 …data active in channel phase 4, valid if data rate is 16 / 8 or 12
100 …data active in channel phase 5 , valid if data rate is 16 or 12
101 …data active in channel phase 6 , valid if data rate is 16 or 12
110 …data active in channel phase 7, valid if data rate is 16 or 12
111 …data active in channel phase 8 , valid if data rate is 16 or 12
8 / 4 or 12 / 6 / 3 MBit/s
12 / 6 / 3 MBit/s
/ 6 MBit/s
/ 6 MBit/s
MBit/s
MBit/s
MBit/s
MBit/s
321
Operational Description T1 / J1
PEB 22554
09.98