PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 262

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

PEB 22554
Functional Description T1 / J1
Violations of these rules are indicated by setting the status bit FRS1.PDEN and the
interrupt status bit ISR0.PDEN. Generation of the interrupt status may be programmed
either with the detection or with any change of state of the pulse density alarm
(GCR.SCI).
Pseudo-Random Bit Sequence Generation and Monitor
15
20
The QuadFALC has the added ability to generate and monitor a 2
-1 and 2
-1 pseudo-
random bit sequences (PRBS). The generated PRBS pattern will be transmitted
optionally inverted or not to the remote end via pins XL1/2 resp. XDOP/N. Generating
and monitoring of PRBS pattern is done according to ITU-T O. 151 and TR62411 with
maximum 14 consecutive zero restriction.
The PRBS monitor senses the PRBS pattern in the incoming data stream.
Synchronization is done on the inverted and non inverted PRBS pattern. The current
synchronization status is reported in status and interrupt status registers. Enabled by bit
LCR1.EPRM each PRBS bit error will increment an error counter (BEC).
Synchronization will be reached within 400 msec with a probability of 99.9% and a BER
of 1/10 (pattern defined by ITU-T O.151).
Semiconductor Group
262
09.98